Processing math: 100%
A 240-GHz Wideband LNA with Dual <span class="MathJax_Preview" style="">- \text{Peak} -G_{\max}</span><script type="math/tex" id="MathJax-Element-1">- \text{Peak} -G_{\max}</script> Cores and Customized High-Speed Transistors in 40-nm CMOS | IEEE Conference Publication | IEEE Xplore

A 240-GHz Wideband LNA with Dual - \text{Peak} -G_{\max} Cores and Customized High-Speed Transistors in 40-nm CMOS


Abstract:

A 240-GHz wideband low-noise amplifier (LNA) incorporating high-speed customized transistors and dual-peak G_{\max} cores is proposed in this work for 6\mathrm{G} app...Show More

Abstract:

A 240-GHz wideband low-noise amplifier (LNA) incorporating high-speed customized transistors and dual-peak G_{\max} cores is proposed in this work for 6\mathrm{G} applications. The customized transistors, designed and modeled using an electromagnetic modeling approach, reduce the gate resistance and the drain-to-gate capacitance, enhancing f_{\max} from 288 to 394 GHz. The \text{dua}1-\text{peak}-G_{\max} core utilizes a reciprocal embedding network consisting of two pre-embedding transmission lines and a DC-isolated Y-embedding transmission line to achieve maximum gain conditions at 221 and 261 GHz simultaneously, enabling the LNA to exhibit wideband characteristics efficiently. Implemented in a 40-nm digital CMOS technology, the proposed LNA shows a measured power gain of 16.2 dB at 220 GHz with a 3-dB bandwidth spanning from 208.6 to 223.6 GHz and a simulated noise figure of 11.5 dB while only consuming 34.7 mW from a 0.9-V supply. The measured output 1-dB compression point is −5.3 dBm at 220 GHz.
Date of Conference: 16-21 June 2024
Date Added to IEEE Xplore: 30 July 2024
ISBN Information:

ISSN Information:

Conference Location: Washington, DC, USA

References

References is not available for this document.