Abstract:
We experimentally demonstrate a novel gate stack engineering technique by introducing a Tunnel Dielectric Layer (TDL) between two Ferroelectric (FE) layers, significantly...Show MoreMetadata
Abstract:
We experimentally demonstrate a novel gate stack engineering technique by introducing a Tunnel Dielectric Layer (TDL) between two Ferroelectric (FE) layers, significantly increasing the Memory Window (MW) in FEFETs. An \gt 2 \mathrm{X} improvement, from 2.9 \mathrm{~V} in the reference device (without TDL) to 7.5 \mathrm{~V} in the 8 / 3 / 8 configuration with TDL, was achieved within NAND thickness limit of 20 \mathrm{~nm} and write voltage \leq 15 \mathrm{~V}. Impact of FE and TDL thickness in MW was also explored.
Date of Conference: 03-06 March 2024
Date Added to IEEE Xplore: 07 May 2024
ISBN Information: