RS5: An Integrated Hardware and Software Ecosystem for RISC- V Embedded Systems

This paper presents RS5, a hardware and software ecosystem designed to provide efficient RISC- V processing in em-bedded systems. While there are many RISC- V implementations available in the literature, RS5 distinguishes itself by offering a modular architecture with optional extensions, such as M (multiplication and division) and Xosvm (memory management), tailoring the core to the specific design needs. RS5 includes optional performance counters for application and core behavior monitoring in real-time, and multitasking support through an OS with a custom memory management mechanism. The Memory Management Unit (MMU) is implemented through a custom register set, offering an alternative to the RISC- V Sv32 extension that may not be well-suited for low-area footprint circuits. The main contribution of this work is the RS5 core, which implements the RISC- V RV32I(M) ISA with OS support to manage external peripherals. Results evaluate the performance of RS5 using a set of benchmarks and compare it to other implementations. Results show that RS5 outperforms other implementations re-garding area and performance. RS5 is publicly-available at https://github.com/gaph-pucrs/RS5.