Abstract:
In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the staged carry save adder (CSA) array, the co...Show MoreMetadata
Abstract:
In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the staged carry save adder (CSA) array, the computation cycles of addition reduced by about 3n/8. In addition, we apply the switch unit to save 2Q-2 registers from the traditional Q-bit CSA. Compare with the original method, the total clock cycles can be reduced by 68% in the case of n=1024 and Q=512 bits.
Published in: Proceedings. IEEE Asia-Pacific Conference on ASIC,
Date of Conference: 08-08 August 2002
Date Added to IEEE Xplore: 07 November 2002
Print ISBN:0-7803-7363-4
Contents 