A Simulation Study of Raised Source Drain Double Gate Junctionless Field Effect Transistor | IEEE Conference Publication | IEEE Xplore

A Simulation Study of Raised Source Drain Double Gate Junctionless Field Effect Transistor


Abstract:

This paper presents a simulation-based study on a raised source drain Junctionless Field Effect Transistor (JLFET). The electrical characteristics of a JLFET structure wh...Show More

Abstract:

This paper presents a simulation-based study on a raised source drain Junctionless Field Effect Transistor (JLFET). The electrical characteristics of a JLFET structure which is having a thinner channel region and thicker source drain regions have been compared with that of a conventional structure. The Ion/Ioff ratio, subthreshold swing and threshold voltages of the two structures– proposed and conventional are compared at 2- D device simulation platform. The simulation results have shown significant improvement in the Ion/Ioff ratio, subthreshold swing of proposed structure.
Date of Conference: 16-18 March 2023
Date Added to IEEE Xplore: 22 May 2023
ISBN Information:
Conference Location: Shillong, India

References

References is not available for this document.