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A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process | IEEE Journals & Magazine | IEEE Xplore

A 10-Gb/s Inductorless Low-Power TIA With a 400-fF Low-Speed Avalanche Photodiode Realized in CMOS Process


Abstract:

Compared with SiGe technology, the limits of low transition frequency and low transconductance per unit current of CMOS technology result in poor noise, narrow bandwidth,...Show More

Abstract:

Compared with SiGe technology, the limits of low transition frequency and low transconductance per unit current of CMOS technology result in poor noise, narrow bandwidth, and high power consumption in high-speed transimpedance amplifiers. The aforementioned issues are further exacerbated while using a low-speed low-cost photodiode. In this study, an equalization technique is proposed to increase the feedback resistance \boldsymbol {R_{F}} , achieving low noise and bandwidth extension of the chip. A novel inductorless bandwidth extension technique is proposed to increase the bandwidth of high-speed channel by 37.5%. In addition, a new current reuse technique is proposed to inject the output stage’s tail current into the input stage to achieve a high gain, saving power consumption by 20%. We achieve 10-Gb/s operation with a 400-fF avalanche photodiode (APD) using 65-nm CMOS technology. The bandwidth is 6.8 GHz, the transimpedance gain is 66 dB \boldsymbol{\Omega } , the average input-referred noise current is 11.9 pA/ \surd Hz, and the average sensitivity is −22.4 dBm at a BER of 1e−12. The SF-TIA chip takes up 0.56 mm2 and consumes 26 mA from a 3.3-V supply.
Page(s): 512 - 521
Date of Publication: 24 January 2023

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