Abstract:
The worst-case output voltage ratio Vs(1)min/Vs(0)maxis derived for a resistor memory matrix having a finite resistance ratio for the bit elements. It is found that the r...Show MoreMetadata
Abstract:
The worst-case output voltage ratio Vs(1)min/Vs(0)maxis derived for a resistor memory matrix having a finite resistance ratio for the bit elements. It is found that the resistance ratio need not be large, and ratios greater than ten are usually sufficient. Input power and output voltage tradeoffs are also discussed.
Published in: IEEE Transactions on Computers ( Volume: C-18, Issue: 10, October 1969)
