Abstract:
A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise performance reflecting the input voltage difference ( \Delta V_{\text {in}} )...Show MoreMetadata
Abstract:
A voltage-controlled oscillator (VCO)-based comparator that automatically adapts its noise performance reflecting the input voltage difference ( \Delta V_{\text {in}} ) is presented. Such adaptive operation significantly reduces the power of high-precision comparators in successive-approximation-register (SAR) ADCs. \Delta V_{\text {in}} is integrated as a time difference via the VCO, where the integration continues as long as the time difference is below a certain threshold, defined by the phase detector deadzone. Thus, when \Delta V_{\text {in}} is large, the comparator operates as a low-power delay line-based comparator, and with small \Delta V_{\text {in}} , the VCO oscillates to integrate the input signal and suppresses the comparator noise. The required oscillations to complete the comparison are inversely proportional to \Delta V_{\text {in}} , realizing fully adaptive noise and power scaling. This article provides a detailed analysis and specific design guidelines of the VCO comparator. Moreover, the PVT drift tolerance and detailed circuit implementations are deeply discussed as well. For proof-of-concept, a 13-bit SAR ADC with the proposed VCO-based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves peak SNDR 66 dB at 1 MS/s with a peak FoM of 29 fJ/conv.-step.
Published in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems ( Volume: 29, Issue: 12, December 2021)