A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving −110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp

A phase interpolator (PI)-free fractional- $N$ sampling phase-locked loop (SPLL) has been proposed and implemented in 130 nm CMOS technology, which eliminates time-domain PI, digital-to-time converter (DTC), or background calibration. This phase-locked loop (PLL) employs two linear slope generators (LSGs) to produce linear waveforms, which are related to the VCO feedback phase. Then the reference directly samples the LSG outputs to obtain the phase error. Following this, a 3 bit DAC-based phase interpolating charge pump (PICP) is utilized to interpolate the phase error before feeding it to the loop filter. This enables the SPLL to achieve a fractional- $N$ ratio without any DTC or calibration. On-chip frequency-modulated continuous-wave (FMCW) chirp generation is also included, which provides 500 MHz FMCW chirp with reconfigurable chirp rate and up to 25% chirp bandwidth to carrier frequency ratio. It consumes 2.8 mW from a 1.2 V supply and occupies an active area of about 0.4 mm². With a 50 MHz crystal reference, the in-band phase noise is measured to be 109 dBc/Hz at 200 kHz offset. The FoM for the system is measured as −243~ −247.5 dB.