An EEG-NIRS Multimodal SoC for Accurate Anesthesia Depth Monitoring | IEEE Journals & Magazine | IEEE Xplore

An EEG-NIRS Multimodal SoC for Accurate Anesthesia Depth Monitoring


Abstract:

In surgical operation environments, anesthesia enables doctors to safe and accurate medical process with minimized movement and pain of patients. In general anesthesia, n...Show More

Abstract:

In surgical operation environments, anesthesia enables doctors to safe and accurate medical process with minimized movement and pain of patients. In general anesthesia, non-invasive and reliable monitoring of anesthesia depth is required because it is directly related to patient's life. However, the current anesthesia depth monitoring approach, bispectral index (BIS), uses only electroencephalography (EEG) from the frontal lobe, and it shows critical limitations in the monitoring of anesthesia depth such as signal distortion due to electrocautery, electromyography (EMG) and dried gel, and false response to the special types of anesthetic drugs. In this paper, a multimodal head-patch system that simultaneously measures EEG and near-infrared spectroscopy (NIRS) on the frontal lobe is proposed. For EEG monitoring, mixed-mode dc-servo loop is proposed to cancel out the ±300-mV electrode-dc offset for dried gel condition with 3.59 noise-efficiency factor. To compensate the electromagnetic noises (EMG and electrocautery) in the system level, NIRS signal is measured. Logarithmic transimpedance amplifier (TIA) and closed-loop controlled (CLC) NIRS current driver are proposed. Logarithmic TIA can reject ambient light up to 10 nA to achieve a 60-dB dynamic range. According to the comparator output, CLC NIRS driver duty cycle can be adjusted from 0.625 m to 50 ms adaptively. The 16-mm2 system-on-chip is fabricated in 65-nm CMOS. It dissipates 25.2-mW peak power. With the combined signals, it can show the clinically important transition from the awake to deep state, but BIS cannot detect the transition in a clinical trial.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 53, Issue: 6, June 2018)
Page(s): 1830 - 1843
Date of Publication: 20 March 2018

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