A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time | IEEE Conference Publication | IEEE Xplore

A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time


Abstract:

In a memory hierarchy, there are various classes of memory systems depending on the access latency. A typical memory hierarchy consists of a CPU cache, DRAM, and an SSD o...Show More

Abstract:

In a memory hierarchy, there are various classes of memory systems depending on the access latency. A typical memory hierarchy consists of a CPU cache, DRAM, and an SSD or HDD. The DRAM has an access latency of 100ns, while flash memory has a latency of about 50μs [1]. Recently, new non-volatile memories with latencies of less than 10μs, including PRAM, MRAM, and ReRAM [2], are getting attention for business-critical systems such as big-data analysis and storage caches. To meet the low latency requirements, a new type of NAND flash, Z-NAND, with a read time (tR) of 3μs has also been introduced [3]. Figure 20.2.1 shows a feature comparison between Z-NAND and conventional 3D NAND [4,5]. The Z-NAND achieves a read time of 3μs, which is 15–20 times faster than conventional NAND. Write throughput reaches up to 160MB/s with a 100μs program time. To further minimize read latency, I/O circuit support a DDR interface for both x8 and x16 mode. To take full advantage of such low-latency memory devices, reduction of memory access overhead is necessary. In this paper, we introduce an NVMe SSD controller which leverages the advantages of the low-latency NAND and enables the reduction of total memory access time, thereby minimizing overall system latency.
Date of Conference: 11-15 February 2018
Date Added to IEEE Xplore: 12 March 2018
ISBN Information:
Electronic ISSN: 2376-8606
Conference Location: San Francisco, CA, USA

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