Design of parity preserving combinational circuits using reversible gate

Parity checking is one of the extensively used approaches for error detection in conventional digital systems. This work presents a 4×4 reversible logic gate (SMS gate) integrated with parity preserving property, which produces all primitive Boolean gates. The hardware complexity in terms of total logic count of SMS gate is 6α+1β only, which found to be minimal compared to all the existing gates. It is shown that the proposed gate provides maximum logical functionalities. Also, three parity preserving combinational circuits are designed in this paper. Designed circuits are implemented using Xilinx ISE 14.7 and the simulation has been performed on ISim simulator.