Abstract:
Reversible computation plays an important role in low power circuit design and efficient energy recycling. In this paper, a switch controlled efficient Reversible Full Ad...Show MoreNotes: This article was mistakenly omitted from the original submission to IEEE Xplore. It is now included as part of the conference record.
Metadata
Abstract:
Reversible computation plays an important role in low power circuit design and efficient energy recycling. In this paper, a switch controlled efficient Reversible Full Adder/Subtractor (RFAS) is presented. RFAS block is further used in the construction of n-bit adder/subtractor. The proposed design is analyzed and compared against the existing reversible techniques. Features such as, hardware cost, logic calculation and gate count etc. are investigated to show the efficiency of the design. Simulation results are verified using Altera Quartus II and ModelSim software. Observations suggest that the circuit offers lesser hardware complexity compared to the existing reversible full adder.
Notes: This article was mistakenly omitted from the original submission to IEEE Xplore. It is now included as part of the conference record.
Published in: 2014 IEEE International Conference on Control System, Computing and Engineering (ICCSCE 2014)
Date of Conference: 28-30 November 2014
Date Added to IEEE Xplore: 21 May 2015
ISBN Information:
