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Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors | IEEE Conference Publication | IEEE Xplore

Optimal algorithm for profile-based power gating: A compiler technique for reducing leakage on execution units in microprocessors


Abstract:

This paper proposes a compiler-based solution to the problem of inserting power gating instructions into code to control activation/deactivation (i.e., ON/OFF) of functio...Show More

Abstract:

This paper proposes a compiler-based solution to the problem of inserting power gating instructions into code to control activation/deactivation (i.e., ON/OFF) of functional units in microprocessor during the code execution, so that the leakage power is maximally saved. Precisely, based on an execution profile of code containing conditional branches and/or loops, we propose a polynomial time optimal algorithm, called PG-instr, of inserting ON/OFF instructions into code with the objective of minimizing the expected total leakage power while considering the power and delay overhead on power gating.
Date of Conference: 07-11 November 2010
Date Added to IEEE Xplore: 03 December 2010
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Conference Location: San Jose, CA, USA

References

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