A bitonic-sorter based VLSI implementation of the M-algorithm

An implementation of the M-algorithm based on a bitonic sorter is proposed for VLSI implementation. The sorting network is already proven. The sorting architecture is well matched to the use of a few high-speed pipelined path extender units. Such units are highly specific to the trellis being decoded, but it is generally possible to fit several on one chip. The architecture is readily extended to larger M with only a small fractional decrease in decoding rate.<>