Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion

In this paper, we propose a bidirectional buffer repeater insertion to reduce the RLC tree delay in multi-source multi-sink systems which involve four significant factors in our works. First, inductance effect is taken into account due to the reason that chip sizes with the exponential reduction and high work frequency. Second, bidirectional buffer repeater could improve interconnect delay more than unidirectional buffer insertion. Third, the location of insertion buffer is also considered in our work. Fourth, more than one buffer could be inserted in critical path while buffers have already existed. Finally, we develop a graphical user interface for designers to estimate the delay with bidirectional buffer repeater insertion target multisource multi-sink systems. Experiment results shown that the reduced delay rate is 50.73% and 64.47% in 0.18 and 0.35 micron fabrication process, respectively.