Time-to-digital converter for RF frequency synthesis in 90 nm CMOS

We propose and demonstrate a 20 ps time-to-digital converter (TDC) in 90 nm digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an all-digital PLL for a fully-compliant GSM transceiver. The TDC core is based on a pseudo-differential digital architecture that makes it insensitive to NMOS and PMOS mismatches. The time conversion resolution is equal to an inverter propagation delay, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with estimation accuracy better than 1%. Measured INL is 0.7 LSB. The TDC consumes 1.3 mA from a 1.3 V supply.