Abstract:
The race to get to the market with high volume quality products demands shorter design to manufacturing cycle forcing increased usage of IPs from multiple sources in SoC ...Show MoreMetadata
Abstract:
The race to get to the market with high volume quality products demands shorter design to manufacturing cycle forcing increased usage of IPs from multiple sources in SoC designs. The shorter time-to-volume (TTV) requires faster silicon bringup with high degree of diagnosability. In an SoC populated with IPs, this is possible only if the IPs can be isolated during test and debug activities. The IEEE standards committee has now developed a new standard IEEE 1500 which defines an isolation mechanism for IPs (cores) whereby cores with 1500 wrapper can be isolated for test and debug on an SoC. This panel from multiple disciplines of electronics industry will debate on the adoption and application of this emerging standard.
Published in: 23rd IEEE VLSI Test Symposium (VTS'05)
Date of Conference: 01-05 May 2005
Date Added to IEEE Xplore: 20 June 2005
Print ISBN:0-7695-2314-5