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HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition | IEEE Journals & Magazine | IEEE Xplore

HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition


Abstract:

Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open...Show More

Abstract:

Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open research area. The two core substructures of HTM are spatial pooler and temporal memory. In this work, we propose a new Spatial Pooler circuit design with parallel memristive crossbar arrays for the 2D columns. The proposed design was validated on two different benchmark datasets, face recognition, and speech recognition. The circuits are simulated and analyzed using a practical memristor device model and 0.18 μm IBM CMOS technology model. The databases AR, YALE, ORL, and UFI, are used to test the performance of the design in face recognition. TIMIT dataset is used for the speech recognition.
Published in: IEEE Transactions on Biomedical Circuits and Systems ( Volume: 11, Issue: 3, June 2017)
Page(s): 640 - 651
Date of Publication: 01 March 2017

ISSN Information:

PubMed ID: 28362614

References

References is not available for this document.