A novel Bi-stable 1-transistor SRAM for high density embedded applications

A 1-transistor SRAM on bulk substrate is presented. The device is fabricated in 28 nm foundry baseline process with an additional buried N-well (BNWL) implant. The unit cell consists of a lateral MOS for memory access operations and intrinsic vertical open-base bipolar structures for self-latch function. The bit cell operation and the disturb immunity are verified at high temperature. Using 28 nm design rules, a unit cell size of 0.025 μm
²
is achieved, offering 80% cell size reduction over 6T-SRAM and providing comparable power and performance.