I. Introduction
The development of high-performance GNSS receive systems becomes challenging if one imposes strict constraints on the available power, chip-size or money budget. As the operation of critical infrastructure like mobile communication systems, electric distribution networks or financial trading systems can depend on correct time synchronization attained through a GNSS receive system, robustness against interference and multi-path propagation is another important requirement that should be met by the receiver design without violating the limitations defined by the available hardware. Under the assumption, that the receive system operates on the basis on an efficient estimation algorithm, two fundamental design options exist in order to attain higher positioning accuracy and robustness against channel imperfections like multi-path propagation or interference. One is to extend the amount of receive antennas, the other is to implement a higher receive bandwidth through a faster temporal sampling rate. However, these alternatives both increase the complexity of the receiver, especially as the ADC forms a bottleneck when heading at a low-complexity design [1]. With multiple receive sensors each antenna requires it's own radio front-end and therefore an individual ADC. High temporal sampling rates become inefficient at high amplitude resolution with output bits as the power dissipation of the ADC increases exponentially .