High speed hardware implementation of an elliptic curve cryptography (ECC) co-processor | IEEE Conference Publication | IEEE Xplore

High speed hardware implementation of an elliptic curve cryptography (ECC) co-processor


Abstract:

We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplic...Show More

Abstract:

We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations, which provide integrated high-throughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.
Date of Conference: 17-19 December 2010
Date Added to IEEE Xplore: 17 February 2011
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Conference Location: Chennai, India

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