VSPEC and its integrated tool suite

In this paper, we describe an integrated tool suite for VSPEC specifications that addresses systems level correctness. The functional correctness of a design is analyzed using the proof obligation generator. The proof obligation generator identifies various properties that must hold for a design to be correct. It then creates a model of the system in the PVS theorem proving language and also generates the properties as theorems to be proved. The performance constraints of the system are analyzed by extracting the relevant information and modeling it as constraint satisfaction problems to be answered by the PDL analyzer. To test the correspondence between the requirements and implementation, test vectors are generated from the specifications and are used in the simulation of the implementation. Using all these tools, it is possible to analyze the correctness of the abstract design and ensure that the implementation satisfies the original requirements.