Guiding intelligent testbench automation using data mining and formal methods

Achieving coverage closure is consistently identified as one of the most difficult challenges during the functional verification of today's HW designs. Constraint random testing as well as coverage directed test generation (CDTG) techniques have been proposed previously with different degree of success. This paper presents a framework for speeding up the coverage closure of the design under verifications (DUV) using state of the art verification techniques. The framework starts with random simulation of the DUV followed by frequent pattern mining of simulation data to extract some valid design constraints. Simulation coverage database is analyzed and the coverage holes are identified and directed to the formal verification step, formal analysis is used to prove the unreachability of some coverage holes during simulation run. Formally proven unreachable cover items as well as automatically extracted design constraints are then fed as test template specification to direct the intelligent testbench generation to rapidly achieve the coverage of previously uncovered corner cases. Our experimental results demonstrate the effectiveness of the proposed approach in closing the coverage loop for a set of today's RTL designs.