Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling

As DRAMs become faster, the penalty to reverse the direction of their data buses increases. Yet, existing real-time memory controllers do not reorder read and write commands. Hence, timing bounds are computed by assuming an alternating pattern of reads and writes, thus accounting for several data bus direction reversals, consequently leading to suboptimal results. Therefore, in this paper, we propose a memory controller that reorders read and write commands, which minimizes reversals. Moreover, we prove through a detailed timing analysis that the effect of the reordering is bounded. Finally, we compare our approach analytically with a state-of-the-art real-time memory controller and show that our timing bounds are up to 27% better.