The hardware design of LDPC decoder in IEEE 802.11n/ac

In this paper, the design of the LDPC decoder architecture in IEEE 802.11n/ac is proposed. The proposed decoder is used to the partial parallel architecture to provide 2 Gbps throughput at 200 MHz clock frequency. In IEEE 802.11n/ac, 12 parity check metrics is provide to support diverse code rates and block lengths. Therefore the network between nodes is configured to be satisfied parity check metrics. However, the structure of the network increases the complexity of LDPC decoder. Hence, the optimized network generator is also proposed to reduce the complexity of the network.