A successive-approximation-register ADC architecture for digital background calibration in high speed ADCs

In this paper, a digital background calibration scheme using an 8-b 10-MS/s successive approximation register (SAR) ADC to calibrate an 8-b 100-MS/s pipelined folding ADC is presented. In order to sample high frequency differential input signals, a new SAR ADC architecture based on the monotonic switching procedure is also proposed. Both ADCs are designed using a 0.18 µm CMOS technology. From the simulation results, it is shown that the SAR ERBW is around 400 MHz and the calibration scheme can reduce offset errors, gain mismatches, and memory effect in the high speed ADC. With Monte Carlo simulation, ENOB, SNDR, and SFDR of the pipelined folding ADC improve 1.75-b, 10.63 dB, and 7.9 dB on average, respectively.