Investigation on High-Performance CMOS With p-Ge and n-InGaAs MOSFETs for Logic Applications

CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (W
_p
/W
_n
). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In
_0.75
Ga
_0.25
As channel with width ratio (W
_p
/W
_n
) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for 5 × 10
¹²
eV
^-1
· cm
^-2
.