A 64-MHz∼640-MHz 64-phase clock generator

This paper proposes a wide-range all-digital phase locked loop (ADPLL) utilizing a successive approximation register-controlled (SAR) architecture. A modified digital to voltage converter (DAC) is adopted to provide a wide supply voltage range for the voltage controlled oscillator (VCO) so that the power consumption of can be reduced and a wide frequency range can be operated. A differential VCO is invented for reducing the jitter. A test chip is implemented using a 0.18μm CMOS process with an area of 500×620um
²
. The measured frequency range is from 64MHz to 640MHz. The p2p jitter is 20.5 ps and the rms jitter is 2.4 ps.