Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator

Substrate noise coupling in RF receiver front end circuitry for LTE wireless communication was examined by full-chip level simulation and on-chip measurements, with a demonstrator built in a 65 nm CMOS technology. A complete simulation flow of full-chip level substrate noise coupling uses a decoupled modeling approach, where substrate noise waveforms drawn with a unified package-chip model of noise source circuits are given to mixed-level simulation of RF chains as noise sensitive circuits. The distribution of substrate noise in a chip and the attenuation with distance are simulated and compare with the measurements. The interference of substrate noise at the 17
^th
harmonics of 124.8 MHz - the operating frequency of the CMOS noise emulator creates spurious tones in the communication bandwidth at 2.1 GHz.