Improved digital design of BPSK modulator using look-up table technique

This paper present a new and improved digital design of BPSK (Binary Phase Shift Key) modulator. The generic digital design of BPSK modulator has two carrier signals in the form of sine wave having 0 degree and 180 degree phase shift. Generic design uses two sine wave generators which act like carrier signal and MUX gives out any one of the carrier signal depending upon the input bit (0 or 1). Our main aim in this paper is to reduce the hardware from the previous existing digital architecture of the BPSK modulator. The new architecture of the BPSK modulator with optimized resource utilization is proposed. In this improved design instead of using two sine wave generators for producing two different sinusoidal carrier signals having 0 degree and 180 degree phase shift, we have used a single sine wave generator using LUTs technique to generate both sinusoidal carrier signals (sine wave with 0 degree and 180 degree phase shift). Digital Clock Manager (DCM) is used a control block (DCM) this make our architecture more flexible and can work on large frequency range. This new improved architecture is implemented using VHDL language on the Xilinx ISE 9.2i simulator. VHDL Design and simulation of every block of the new architecture is done. Finally the simulation of whole digital design of BPSK is performed and it's gives the satisfactory result which confirms that the new architecture can produce BPSK modulated signal.