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SECTION I

## INTRODUCTION

THE decision of the world's leading integrated circuit (IC) manufacturer Intel to alter the architecture of the traditional metal-oxide-semiconductor, field-effect transistor (MOSFET) from planar to FinFET1 (TriGate) [1] is considered the most dramatic change that has occurred in the IC industry over the past 40 years [2]. By adding only three percent to the fabrication cost, Intel's TriGate process, “Ivy Bridge,” is now in volume production. Intel's next 22-nm TriGate, system-on-chip (SoC) technology [which offers a variety of transistor choices for high-performance, low-power, and high-voltage applications] is expected to have a 20–60 percent performance improvement and a reduction of four orders of magnitude in the leakage current over the former 32-nm planar process [3]. Since Intel had had a significant lead over its competitors in the past, it was anticipated that other major IC manufactures follow suit and adopt the FinFET process. This prediction turned out to be true soon afterwards when the world's two largest IC foundries, TSMC and GLOBALFOUNDRIES (GFs), announced their plans to switch to 16-nm [4] and 14-nm [5] FinFET technologies, respectively.

However, university and industry experts believe that the Si FinFET is just one possible option and there are multiple uncertain paths ahead. The ultra-thin body (UTB) silicon-on-insulator (SOI) transistor by ST Microelectronics [6] and the deeply depleted channel MOSFET by SuVolta [7] are close competitors to the FinFET architecture. IBM has also aggressively advanced the planar MOSFET by scaling it down to the 10-nm node [8]. Alternatively, materials like Ge (also suitable for optical interconnects) [9], III-V compound semiconductors like InGaAs [10], monolayer semiconductors such as graphene [11] and MoS2 [12] (which naturally form UTB transistors), and transistors with nonclassical operating modes (including tunnel field-effect transistors (TFETs) [13] and negative capacitance transistors [14]) are among the long-term proposed resolutions. Another interesting possible scenario might be to combine the alternative architectures, materials, and operating modes to create various building blocks such as FinFET/UTB SiGe/III-V transistors [15] and FinFET/Pillar SiGe/III-V TFET [16].

Compact models for semiconductor devices are essential for all types of electronic designs. Analog, digital, or mixed-signal circuits are always carefully implemented and tested by circuit simulators where compact models are used to represent, in a mathematical form, the electronic behavior of each device. BSIM2 compact models for MOSFETs have served industry for more than two decades now; this started with BSIM3, and later, BSIM4 and BSIMSOI. BSIM4, the industry-standard planar MOSFET model, has been widely used by Electronic Design Automation (EDA) and IC manufacturing companies from the 0.18-$\mu{\rm m}$ node to the current 20-nm node. Indeed, it would not be an exaggeration to say that the advances in information technology that have taken place over the last decade have significantly benefited from BSIM models. Research and development in the BSIM Group continues to support a majority of the aforementioned scenarios for complementary metal–oxide–semiconductor (CMOS) technology by developing device architecture-dependent, material-independent compact models. Recently, the BSIM Group has developed “BSIM-CMG” to model common double-, triple-, quadruple-, and surround-gate FinFETs, and “BSIM-IMG” to model independent double-gate MOSFETs and capture the resulting threshold voltage $(V_{{\rm th}})$ adjustment with back gate bias. These two models are the focus of this paper. In March 2012, the Compact Model Council (CMC) selected BSIM-CMG as the first and only industry-standard model for the FinFET. BSIM-IMG is also under consideration by CMC as a standard model for UTB-SOI technology.

This paper is organized as follows: Section II briefly reviews the historical path to make very short-channel MOSFETs and the evolvement of BSIM compact models throughout these years; readers who wish to focus on the models can skip this section. Sections III and IV provide details on BSIM-CMG and BSIM-IMG models, respectively. The conclusions of the paper are summarized in Section V.

SECTION II

## SHORT-CHANNEL MOSFETS, NEW DEVICE ARCHITECTURES AND COMPACT MODELS

The ability to continually and reliably reduce the physical size of Si MOSFETs has continually improved their speed and power efficiency, and hence the speed and power efficiency of a multitude of electronic devices, from cellular phones to personal computers. For the last two decades, the understanding in the field was that conventional planar bulk MOSFET scaling could not continue forever at the same rate of Moore's law [17], [18], [19], [20]. Shrinking the gate length $L_{g}$ degrades the transfer characteristics of a planar MOSFET; the subthreshold swing $SS$ degrades and $V_{{\rm th}}$ decreases [17] (the effect known as $V_{{\rm th}}$ roll-off), which implies that the device cannot be turned off easily by lowering the gate voltage, $V_{g}$. These problems are collectively known as short-channel effects (SCEs) [21]. Because of SCEs, the device characteristics become increasingly sensitive to $L_{g}$ variations and process induced variability turns out to be more problematic. Early theoretical and modeling approaches to study SCEs included those of Yau [22], Liu et al. [23], and Troutman [24]. The historical solution to this problem has been to increase the gate control by reducing the gate oxide/high-k dielectric thickness in proportion to $L_{g}$.

In the early 1990s, it was observed that at gate lengths below 20 nm, leakage paths several nanometers below the silicon-dielectric interface (sub-surface leakage paths) are primarily responsible for the leakage current. These paths are weakly controlled by the gate (even with an ideal “zero” oxide thickness) and their potential barriers can be easily lowered by ${V}_{d}$ through the enhanced electric field coupling to the drain (the effect known as drain induced barrier lowering or DIBL). This new challenge to $L_{g}$ scaling has demanded a great deal of effort and resources to engineer the substrate doping (i.e., create retrograde and super steep retrograde profiles), form shallow source and drain extensions, and add halo (pocket) implants under the source and drain extensions.

Considering the fact that the scaling of planar MOSFETs is becoming more difficult and more expensive, for the last two decades worldwide research in electronics has focused a major thrust to explore alternative device architectures and materials [9], [10], [11], [12], [13], [14], [15], [16], [25].

### A. New Device Architectures

One approach to surmount the impending $L_{g}$ scaling barrier is to preserve as much of present-day technology as possible, and to augment it with new device architectures that could allay some or most of the problems that appear in scaled planar MOSFETs, including undesirable leakage currents and excessive static power. Among these alternative architectures are FinFET [3], [26], [27], [28], [29], [30], [31], [32] and UTB [33], [34], [35], [36]. Both of these structures can eliminate the leakage paths that are far from the gate(s) by limiting the presence of semiconductor body in the immediate vicinity of the gate(s).

Fig. 1 shows a double-gate MOSFET whose body consists of a thin film of undoped silicon. If the body is thin, any lines drawn between the source and drain (including possible leakage paths) would not be far from one of the gates. In this structure, channel doping is not needed for suppressing SCEs. Thus, random dopant fluctuation, a major contributor to device variation, is eliminated [37].

Fig. 1. A double-gate MOSFET with an undoped thin film Si body. (The source and drain spacers and contacts have not been shown). The sub-surface leakage paths are close to the gates and SCEs can be very well suppressed [44].

The FinFET in Fig. 2 is one of the manufacturable versions of the multi-gate (MG) structure in Fig. 1. The fin can be constructed on SOI or on lower-cost bulk substrates with the usual patterning and etching technologies. If the fin is thin enough, with a thickness $T_{\rm fin}$ smaller than ${L}_{g}$, SCEs are very well suppressed and $SS$ is close to the ideal value of $\sim {60} {\rm mV}/{\rm decade}$ at room temperature (seeFig. 4 in [3]). This new architecture resulted in a new scaling rule, i.e., $L_{g}$ can be scaled by maintaining the condition $T_{\rm fin}\sim<L_{g}$, relaxing the scaling of gate dielectric and body doping. Hu et al. reported 45- and 18-nm working double-gate FinFETs in 1998 and 1999 [26], [27]. Soon after, 10-nm double-gate [28], 10-nm triple-gate ($\Omega$ gate) [29], 5-nm nanowire [30], and 3-nm quadruple-gate (all-around gate) [31] FinFETs were reported by IC manufacturer AMD, Leti research institute, TSMC, and Korea Advanced Institute of Science and Technology, respectively.

Fig. 2. The FinFET is a 3D structure and it benefits from a larger electrical area than physical foot-print because the channel width W is twice the fin height ${\rm H}_{\rm fin}$ plus the fin thickness ${\rm T}_{\rm fin}$ and W is larger than the fin pitch.
Fig. 3. Schematic of a UTB transistor. The body can be a thin film of silicon, or a monolayer semiconductor like graphene [11], ${\rm MoS}_{2}$ [12], and ${\rm WSe}_{2}$ [40]. If the buried oxide BOx is thin, the substrate can be used to bias the body for a desired dynamic ${V}_{{\rm th}}$ shift.
Fig. 4. Semiconductor technology-IC design interaction along the different phases of product development.

In an analogous manner, if the thickness of the silicon film $T_{{\rm si}}$ in a silicon-on-insulator (SOI) MOSFET is only several nanometers (thinner than about one half of $L_{g}$), the leakage paths far from the gate will be eliminated and SCEs can be significantly suppressed; indeed, the transistor leakage current is reduced by $\sim {10} {\rm X}$ for every nanometer drop in $T_{{\rm si}}$ (see Fig. 1 of [33]). The UTB-SOI MOSFETs require SOI substrates with extremely uniform silicon films (sub-nanometer uniformity). In 2009, SOI wafer supplier, Soitec, overcame the challenge through a process called “Smart Cut” and developed SOI wafers with a desired tolerance of $\pm {0.5} {\rm nm}$ [38]. It is worth mentioning that UTB-SOI MOSFETs with $T_{{\rm si}}$ as thin as 3 nm has been experimentally realized [39]. In the long-term future, the most attractive channel materials are the monolayer semiconductors such as graphene [11] and ${\rm MoS}_{2}$ [12] and they naturally form UTB transistors. Monolayer ${\rm WSe}_{2}$ transistor with 60 mV/decade subthreshold swing has recently been demonstrated [40].

If the thickness of the Buried Oxide (BOx) in a UTB transistor is reduced, the substrate immediately below the BOx can be used as a back gate to bias the body and enable a multi-$V_{{\rm th}}$ technology [41], [42]. The structure with a reduced BOx is referred to as “ultra-thin body and BOx” (UTBB) and recently it has been of particular interest to SoC designers [43]. Fig. 3 shows a UTB transistor with body-bias capability.

### B. Compact Modeling

With increasing technology complexity and need for ever-decreasing time to market for electronic products from newer technology nodes, IC design and technology development cannot remain de-coupled. Unlike in the past where product development happened after technology maturity to benefit from high yields, today IC design houses closely collaborate and engage with their foundry partners as much as three years prior. Product definition and IP development begin even before the availability of the first silicon hardware results. The exchange of information between the two parties (see Fig. 4) happens at a number of stages from product definition to final product validation through a set of technology definitions called a process design kit (PDK). Compact SPICE models are a fundamental part of a PDK.

A compact model for a semiconductor device is a concise mathematical description of its complex behavior, and it is usually implemented in a computer programing language like C or Verilog-A. Despite the fact that the implementation might consist of thousands of lines of codes, it takes only a fraction of a millisecond for computer simulation tools like SPICE [45] to run the code (for one transistor at a single bias point). In addition, the model's accuracy and quality is of paramount importance. We could safely say that IC design is the only engineering field where we aim for “first time right” designs in order to stay competitive. The speed and accuracy ($\sim {1\%}$ RMS error after calibration to experimental data) of the BSIM family of compact models enable simulation tools to verify the functionality and performance of ICs (containing millions of transistors) before an expensive fabrication process takes place. The models are also flexible enough to accommodate technology modifications from multiple foundries. The models undergo continuous innovation with fundamental contributions from universities and important incremental contributions from industry leading to their deployment.

### C. BSIM Family of Compact Models

The BSIM Group started device modeling in the C language in the 1980s and since then it has been working to advance the modeling for IC designs. The first two models, BSIM1 [46] and BSIM2 [47], were the beginning of MOSFET modeling in the group. The BSIM1 model emphasized accuracy, computational efficiency, and a parameter extraction procedure using a semi-empirical approach, as opposed to a pure physics-oriented modeling. BSIM2 was an extension to BSIM1 where attention was paid to the first-order derivatives of the terminal currents and charges with respect to the terminal voltages, thereby making the model applicable for analog circuit design. The BSIM3 model [48], [49], [50] employed advanced smoothing functions, which resulted in continuous expressions for currents, charges, and their higher-order derivatives; this progress eliminated the discontinuities in I-V and C-V simulations and sped up the convergence in SPICE. BSIM3 was selected as the world's first industry-standard model for IC design by CMC in 1997 and it is still used in production level PDKs, especially for the 0.18-$\mu{\rm m}$ node and older technologies.

The next generation BSIM4 model [50], [51] benefited from major updates, including several new submodels for emerging physical effects (e.g., gate tunneling current) and layout effects (e.g., well proximity effect), radio-frequency (RF) enhancements (e.g., gate and substrate resistance networks), an advanced thermal noise model (i.e., Holistic Noise model).

Around the same time as BSIM4 development, the BSIM Group also worked on developing BSIMSOI, a compact model for SOI MOSFETs covering both partially and fully depleted SOI structures. The BSIMSOI model was standardized in 2001.

BSIM models consist of two main components: a basic model and a set of real-device submodels. The basic model is an ideal long-channel model. The real-device submodels are physically derived expressions that are added appropriately around the basic model to capture the correct behavior of short-channel devices. Further discussion on these effects will be presented in the upcoming sections.

To address BSIM4's symmetry problem around $V_{{\rm ds}}=0$, the BSIM Group started the BSIM6 project in late 2010. BSIM6 has a charge-based basic model with all the real-device submodels adapted from BSIM4, while guaranteeing symmetry around $V_{{\rm ds}}=0$ [52]. The model fulfills all quality tests including McAndrew-Gummel symmetry and ac symmetry tests [53]; additionally, it provides correct slopes for RF higher-order distortion analysis using harmonic balance simulation [54]. To enable a smooth transition from BSIM4, we have also outlined a unique sequential RF model extraction procedure using BSIM6 [55]. In April 2013, CMC approved the BSIM6 model as an analog and RF friendly continuation to the BSIM4 model.

As the FinFET and UTB transistors are finding their way into the market, accurate, and computationally efficient models that predict the complex dc and ac behaviors of these transistors in ICs are essential. The project of developing compact models for MG transistors started in 2005. BSIM-CMG targeted the class of common MG (CMG) FinFETs, while BSIM-IMG targeted independent MG (IMG) structures where asymmetric front and back gates are allowed. The previously mentioned UTB and UTBB transistors are examples of the structures that can be simulated by the BSIM-IMG model. Fig. 5 shows the timeline of the BSIM family of compact models.

Fig. 5. The timeline of the BSIM family of compact models. The models in gray (BSIM1-3 and BSIM5) are not supported by the group any longer. The underlined model (BSIM-IMG) IS under evaluation/standardization by CMC.

A list of other CMC industry-standard models is as follows: 1) Bulk MOSFET models: PSP by Arizona State University and HiSIM by Hiroshima University; 2) SOI MOSFET models: HiSIM_SOI by Hiroshima University; 3) High-Voltage MOSFET models: HiSIM_HV by Hiroshima University; 4) Bipolar Transistor models: HICUM by Dresden University of Technology and MEXTRAM by Delft University of Technology.

SECTION III

## BSIM-CMG MODEL

BSIM-CMG is a surface potential-based model where all the quantities of interest, such as the terminal currents and charges, are calculated from the surface potentials at the source and drain ends of the channel. Fig. 6 shows the MG FinFETs that can be simulated with the BSIM-CMG model. Similar to the other BSIM models, BSIM-CMG has two main components: first, a basic model and second, a set of real-device submodels to augment the basic model. The BSIM-CMG model is a CMC industry-standard model, and all the following standardization requirements have been met: SCEs, Quantum mechanical effects (QMEs), channel length modulation, electric-field dependent mobility, geometric scaling in three dimensions, front gate tailoring including the ability to support poly gate depletion (PDE) and a metal gate, current saturation, impact ionization, temperature scaling, self-heating, gate leakage, noise models, geometrically scalable parasitic models for extrinsic resistances and capacitances. Fig. 7 illustrates the structure of the BSIM-CMG model.

Fig. 6. The different MG FinFETs that can be simulated by BSIM-CMG. The parameter GEOMOD selects the geometry, BULKMOD selects the substrate (SOI or bulk), and ASYMMOD enables an asymmetric I-V.
Fig. 7. The structure of the BSIM-CMG model. Not all submodels are shown. QMEs: quantum mechanical effects; PDE: gate poly depletion effect; Series R: series resistances; Current Sat.: current saturation; Mobility Deg.: carrier mobility degradation; GIDL/GISL: gate induced drain/source leakage.

### A. Basic Model: Poisson-Carrier Transport

The BSIM compact models are based on a basic model that is obtained using a long-channel assumption (also called the gradual-channel approximation GCA [56]), and assuming that other physical effects, such as mobility degradation, can be neglected. Several basic models have been proposed for the FinFET, where charge [57] and surface potential [58], [59] modeling approaches have been mainly used in the derivation. The basic model used in BSIM-CMG is based on a solution of Poisson-drift/diffusion equations for a long-channel double-gate FinFET, assuming a finite doping in the channel to mimic the doped channels currently used in FinFET fabrication [3]. Finally, the basic model developed for BSIM-CMG agrees with the results of commercial 2-D numerical device simulators without the use of fitting parameters [59], [60].

#### 1) Electrostatics

The structure shown in Fig. 8, which consists of a 2-D cross-section of a common double-gate transistor similar to that in Fig. 1, is used as a reference for the model derivation. Poisson's equation, assuming GCA, Boltzmann's distribution for the inversion carriers, and considering only mobile carries (e.g., electrons in an NMOS FinFET), is written as: TeX Source $${{\partial^{2}\psi\left(x,y\right)}\over{\partial x^{2}}}={{q}\over{\varepsilon_{\rm fin}}}\left({n_{i}e}^{{\psi\left(x,y\right)-\phi_{B}-V_{{\rm ch}}(y)}\over{V_{{\rm tm}}}}+N_{\rm body}\right)\eqno{\hbox{(1)}}$$ where the symbols are as follows: $\psi (x,y)$ is the electrostatic potential in the channel; $q$ is the magnitude of the electronic charge; $n_{i}$ is the intrinsic carrier concentration; $\varepsilon_{\rm fin}$ is the dielectric constant of the channel (fin); $V_{{\rm tm}}$ is the thermal voltage given by $k_{B}T/q$, where $k_{B}$ and $T$ are the Boltzmann constant and the temperature, respectively; $V_{{\rm ch}}$ is the quasi-Fermi potential of the channel ($V_{{\rm ch}}(0)=V_{{\rm s}}$ and $V_{{\rm ch}}(L)=V_{d}$); $N_{\rm body}$ is the body doping; $\phi_{B}=V_{{\rm tm}}\ln (N_{\rm body}{/}n_{i})$.

Fig. 8. Schematic of the symmetric, common double-gate transistor under study.

In order to obtain the potential in the channel, $\psi$ is written as TeX Source $$\psi\left(x,y\right)\cong\psi_{1}\left(x,y\right)+\psi_{2}\left(x,y\right)\!.\eqno{\hbox{(2)}}$$ Here, $\psi_{1}$ is the potential contribution due to the inversion carriers and without the effect of the ionized dopants $N_{\rm body}$, and is given by TeX Source $$\partial^{2}\psi_{1}(x,y)/\partial x^{2}=qn_{i}/\varepsilon_{\rm fin}e^{{\psi_{1}\left(x,y\right)-\phi_{B}-V_{{\rm ch}}(y)}\over{V_{{\rm tm}}}}\eqno{\hbox{(3)}}$$ and $\psi_{2}$ is the potential contribution due to the presence of the ionized dopants $N_{\rm body}$, and without the effect of the inversion carriers, and is given by TeX Source $$\partial^{2}\psi_{2}(x,y)/\partial x^{2}=qN_{\rm body}/\varepsilon_{\rm fin}.\eqno{\hbox{(4)}}$$ Using the fact that the vertical component of the electric field $\xi_{x}$ at the center of a symmetric double gate structure is zero, we can integrate (3) twice to obtain $\psi_{1}(x,y)$ as a function of the potential in the center of the body $\psi_{0}(y)$: TeX Source \eqalignno{&\psi_{1}\left(x,y\right)=\psi_{0}\left(y\right)\cr &\hskip1.2em-2V_{{\rm tm}}\ln \left[\cos\left(\sqrt{{{q}\over{2\varepsilon_{\rm fin}V_{{\rm tm}}}}{{n_{i}^{2}}\over{N_{\rm body}}}e^{{\psi_{0}\left(y\right)-V_{{\rm ch}}\left(y\right)}\over{V_{{\rm tm}}}}}\!\times\!{{x}\over{2}}\right)\right]\!.\cr&&{\hbox{(5)}}}

Applying $\xi_{x}=0$ at the center of the channel, setting $\psi_{2}\left(x=0,y\right)=0$, and integrating (4) twice, it is possible to obtain TeX Source $$\psi_{2}\left(x,y\right)=qN_{\rm body}x^{2}/(2\varepsilon_{\rm fin}).\eqno{\hbox{(6)}}$$

The surface potential $\psi_{s}$ at any point $y$ along the surface is obtained by evaluating the sum of $\psi_{1}$ and $\psi_{2}$ at the surface: TeX Source $$\psi_{s}\left(y\right) \cong \psi_{1}\left(-T_{\rm fin}{/2,}y\right)+\psi_{2}\left({-T}_{\rm fin}{/2,}y\right)\!.\eqno{\hbox{(7)}}$$

Gauss's law and the boundary conditions at the channel interface lead to a second important equation TeX Source $$V_{{\rm gs}}=V_{\rm fb}+\psi_{s}\left(y\right)+\varepsilon_{\rm fin}\xi_{\rm xs}/C_{\rm ox}\eqno{\hbox{(8)}}$$ where the symbols are as follows: $V_{{\rm gs}}$ is the gate voltage; $V_{\rm fb}$ is the flat-band voltage; $C_{\rm ox}$ is the gate oxide capacitance per unit area, given by $\varepsilon_{\rm ox}/T_{\rm ox}$, where $\varepsilon_{\rm ox}$ and $T_{\rm ox}$ are the oxide dielectric constant and oxide thickness, respectively; $\xi_{\rm xs}$ is the vertical component of the electric field at the surface, which can be obtained by integrating (1) as TeX Source $$\xi_{\rm xs}=\sqrt{{{2qn_{i}}\over{\varepsilon_{\rm fin}}}\left({\matrix{V_{{\rm tm}}\left(e^{{\psi_{s}\left(y\right)}\over{V_{{\rm tm}}}}-e^{{\psi_{0}\left(y\right)}\over{V_{{\rm tm}}}}\right)e^{{-\phi_{B}-V_{{\rm ch}}\left(y\right)}\over{V_{{\rm tm}}}}+\hfill\cr e^{{\phi_{B}}\over{V_{{\rm tm}}}}\left(\psi_{s}\left(y\right)-\psi_{0}\left(y\right)\right)\hfill}}\right)}.\eqno{\hbox{(9)}}$$ Equations (7) and (8) represent a self-consistent system of equations that can be used to obtain $\psi_{0}$ and $\psi_{s}$; however, through a change of variable, they can be written as a single equation: TeX Source \eqalignno{& f\left(\beta\right)\equiv\ln\left(\beta\right)-\ln{\left(\cos\left(\beta\right)\right)-{{V_{{\rm gs}}-V_{\rm fb}{-V}_{{\rm ch}}}\over{2V_{{\rm tm}}}}}\cr &\hskip4em+\ln \left({{2}\over{T_{\rm fin}}}\sqrt{{2\varepsilon_{\rm fin}V_{{\rm tm}}N_{\rm body}}\over{qn_{i}^{2}}}\right)+{{2\varepsilon_{\rm fin}}\over{T_{\rm fin}C_{\rm ox}}}\cr &\times\!\sqrt{\!\!\beta^{2}\!\!\left({{e^{{\psi_{\rm pert}}\over{V_{{\rm tm}}}}}\over{{\rm cos}^{2}\!\left(\beta\right)}}\!-\!1\!\!\right)\!+\!{{\psi_{\rm pert}}\over{V_{{\rm tm}}^{2}}}\!\left(\psi_{\rm pert}\!-\!{2V}_{{\rm tm}}\ln \left(\cos\left(\beta\right)\right)\right)}\!=\!0\cr&&{\hbox{(10)}}} where $\beta$ is the argument of the cosine function in $\psi_{1}(T_{\rm fin}/2,y)$ and $\psi_{\rm pert}$ is $\psi_{2}(T_{\rm fin}/2,y)$.

Equation (10) (implicit in $\beta$) is the basic surface potential equation (SPE) in BSIM-CMG. It is solved by first using an analytical approximation for the initial guess [60], followed by two Householder's cubic iterations (3rd order Newton-Raphson iterations); together these make the model numerically robust and accurate. The surface potentials at the source end $\phi_{s}$ and drain end $\phi_{d}$ are calculated by setting $V_{{\rm ch}}=V_{s}$ and $V_{{\rm ch}}=V_{d}$, respectively. For a lightly doped body, (10) can be simplified further [61] to speed up the simulation by approximately 25%. This option can be selected in the BSIM-CMG model by setting the parameter COREMOD. A separate SPE has been derived for the cylindrical gate geometry, which has been discussed in detail in [62].

#### 2) Transport

The drain to source current $I_{{\rm ds}}$ for a long-channel double-gate FinFET is obtained from a solution of the drift-diffusion equation TeX Source $$I_{{\rm ds}}\left(y\right)=\mu\left(T\right)WQ_{{\rm inv}}(y){{dV_{{\rm ch}}}\over{dy}}\eqno{\hbox{(11)}}$$ where $\mu\left(T\right)$ is the low-field and temperature-dependent mobility, $W$ is the total effective width, and $Q_{{\rm inv}}$ is the inversion charge per unit area in the upper half part of the body. Equation (11) includes drift and diffusion transport mechanisms through the use of the quasi-Fermi potential.

Integrating both sides of (11), and considering the fact that under quasi-static operation $I_{{\rm ds}}$ is constant along the channel, it is possible to express (11) in its integral form: TeX Source $$I_{ds}={{W}\over{L}}\mu\left(T\right)\int^{Q_{\rm invd}}_{Q_{invs}}Q_{{\rm inv}}\left[{{dV_{{\rm ch}}}\over{dQ_{{\rm inv}}}}\right]dQ_{{\rm inv}}\eqno{\hbox{(12)}}$$ where $L$ is the effective channel length, $Q_{\rm invs}$ and $Q_{\rm invd}$ are the inversion charge densities at the source and drain ends, respectively, given by TeX Source $$Q_{\rm invd/s}=C_{\rm ox}\left(V_{{\rm gs}}-V_{\rm fb}-\phi_{d/s}\right)-{\rm Q}_{\rm bulk}.\eqno{\hbox{(13)}}$$ Here, $Q_{\rm bulk}$ is the fixed depletion charge and is given by $qN_{\rm body}T_{\rm fin}$. The term $dV_{{\rm ch}}/dQ_{{\rm inv}}$ in (12) can be calculated as a function of $Q_{{\rm inv}}$ using a simple—but accurate—implicit equation for $Q_{{\rm inv}}$ [60]: TeX Source $$Q_{{\rm inv}}\left(y\right)=\sqrt{2qn_{i}\varepsilon_{\rm fin}V_{{\rm tm}}}.e^{{\psi_{s}\left(y\right)-\phi_{B}-V_{{\rm ch}}(y)}\over{{2V}_{{\rm tm}}}}\sqrt{{Q_{{\rm inv}}\left(y\right)}\over{Q_{{\rm inv}}\left(y\right)+Q_{0}}}\eqno{\hbox{(14)}}$$ where ${\rm Q}_{0}={\rm Q}_{\rm bulk}{\rm+5}{\rm C}_{\rm fin}{\rm V}_{{\rm tm}}$, with ${\rm C}_{\rm fin}={\varepsilon}_{\rm fin}{/}{\rm T}_{\rm fin}$. Equation (12) can be integrated analytically using (14) to calculate $dV_{{\rm ch}}/dQ_{{\rm inv}}$, leading to the following basic equation for $I_{{\rm ds}}$: TeX Source \eqalignno{I_{{\rm ds}}=&\,\mu\left(T\right)\cdot{{W}\over{L}}\cdot\Bigg [{{Q_{inv,s}^{2}-Q_{inv,d}^{2}}\over{2C_{\rm ox}}}+{2V}_{{\rm tm}}\left(Q_{{\rm inv,s}}-Q_{{\rm inv,d}}\right)\cr &\qquad\qquad\quad -V_{{\rm tm}}Q_{0}\ln \left({{Q_{0}+Q_{{\rm inv,s}}}\over{Q_{0}+Q_{{\rm inv,d}}}}\right)\Bigg].&{\hbox{(15)}}}

### B. Real-Device Effects

This subsection briefly reviews some of the real-device effects for the modern MG transistors, highlighting the key physical effects and implementations, and outlining the proper references for further details.

#### 1) Short-Channel Effects

Short-channel effects, as discussed in Section II, mainly originate from the 2-D electrostatics and degrade the transistor performance through $V_{{\rm th}}$ roll-off and $SS$ degradation.

##### $V_{{\rm th}}$ Roll-Off

A quasi-2-D electrostatic analysis (i.e., including both the lateral and vertical field components $\xi_{x}$ and $\xi_{y}$ but ignoring the $y$ dependence of $\xi_{x}, x$ dependence of $\xi_{y}$, and inversion carriers) is performed on a double-gate structure to find the minimum of the potential in the center of the channel $\psi_{0}\left(y\right)$; this potential corresponds to the top of the barrier. The calculated potential $\phi_{\rm c,min}$ [60] is a function of the terminal voltages $V_{{\rm gs}}$ and $V_{{\rm ds}}$, $L$, and the so-called characteristic field penetration length $\lambda$, defined as TeX Source $$\lambda\equiv \sqrt{{{\varepsilon_{\rm fin}}\over{{2}\varepsilon_{\rm ox}}}\left({1+}{{\varepsilon_{\rm ox}T_{\rm fin}}\over{{{4}\varepsilon}_{\rm fin}T_{\rm ox}}}\right)T_{\rm fin}T_{\rm ox}}.\eqno{\hbox{(16)}}$$ Also known as the natural length, $\lambda$ shows to what extent the electric field from the drain can penetrate into the channel and hence how it influences the source-to-channel potential barrier.

The change in $V_{{\rm th}}$ is then defined as TeX Source $${{\Delta}V}_{{\rm th}}\left(L,{\lambda,V}_{{\rm ds}}\right)\equiv \lim_{L\rightarrow\infty}{\phi_{\rm c,min}\left(L,{\lambda,V_{{\rm gs}},V}_{{\rm ds}}\right)}.\eqno{\hbox{(17)}}$$

The term ${{\Delta}V}_{{\rm th}}(L\lambda V_{{\rm ds}})$ is further enhanced with more parameters to ease the parameter extraction procedure and increase the accuracy [51]. In BSIM-CMG model, ${{\Delta}V}_{{\rm th}}$ is subtracted from $V_{\rm fb}$.

##### $SS$ Degradation

Subthreshold swing, $SS$, in a planar MOSFET can be defined as TeX Source \eqalignno{SS\equiv&\,\left({{d\left[\log\left(I_{ds}\right)\right]}\over{dV_{gs}}}\right)^{-1}\cr\cong &\,\ln\left({10}\right)\times V_{{\rm tm}}\left({1+}{{C_{\rm dep}}\over{C_{\rm ox}}}+{{C_{\rm IT}}\over{C_{\rm ox}}}{\rm+}{{C_{\rm DSC}}\over{C_{\rm ox}}}\right)&{\hbox{(18)}}} where $C_{\rm dep}$ is the depletion capacitance associated with the depletion region, $C_{\rm IT}$ is the capacitance due to interface states, and $C_{\rm DSC}$ is the coupling capacitance between source/drain to channel, which has similar $L$, $\lambda$, and $V_{{\rm ds}}$ dependencies as ${{\Delta}V}_{{\rm th}}s$ discussed above. The degradation in subthreshold swing is then modeled through a modification in $V_{{\rm tm}}$ TeX Source $${nV}_{{\rm tm}}\equiv {\left({1+}{{C_{\rm dep}+C_{\rm IT}+C_{\rm DSC}}\over{C_{\rm ox}}}\right)}V_{tm}\eqno{\hbox{(19)}}$$ where ${nV}_{{\rm tm}}$ is substituted for $V_{{\rm tm}}$ in all bias-dependent calculations.

#### 2) Quantum Mechanical Effects

The quantum mechanical confinement of the inversion carriers (which can be structural due to the thin body or electrical due to band bending near the surface) increases the device $V_{{\rm th}}$, degrades the gate capacitance, and reduces the effective width of the device [see Fig. 9(a)] due to a shift in the inversion charge centroid [60]. A shift in the bottom of the conduction/valence band due to the structural confinement, given by [Eq. 2.54, [60]] is used to modify $V_{{\rm ch}}$ at the source and drain SPEs. To model electrical confinement, the bias-dependent charge centroid thickness $T_{\rm cen}$ [see Fig. 9(b)] is used to modify the gate insulator thickness and calculate the reduction in the width of the device [63]. The simulation results are in an excellent agreement with those calculated from a self-consistent, Schrödinger-Poisson approach.

Fig. 9. (a) Quantum structural and electrical confinements in the fin re-distribute the Fin, re-distributes the charge away from the interface. (b) With increasing gate bias, the charge centroid tends to move closer to the interface [63].

Degradation of carrier mobility in the FinFET occurs due to four main scattering events: Coulomb scattering, acoustic phonon scattering, surface roughness scattering, and optical phonon scattering. The first three scattering mechanisms have vertical (transverse) field dependency and they are each dominant at different regions of operation: Coulomb scattering at weak inversion, acoustic phonon scattering at mid-inversion, and surface roughness scattering at strong inversion. Together, they are modeled through a submodel called “low-field mobility degradation” and used to get the effective mobility [51].

At high lateral field (i.e., at high drain biases and short channels), the dominant scattering mechanism is optical phonon scattering since the electrons are able to gain enough energy to emit optical phonons. This high-field scattering causes the velocity of carriers to saturate; the effect is calculated via a submodel called “current saturation” and it degrades the drain to source current directly [51].

#### 4) Series Resistances

From a device architecture perspective, one of the challenges in thin body transistors is the large series (parasitic) resistances. For this reason, in the FinFET and UTB transistors, the source and drain silicon is enlarged (raised) to reduce resistances. As shown in Fig. 10(a), the parasitic source/drain resistance submodel in BSIM-CMG includes a bias-dependent extension resistance $R_{\rm ext}$, a spreading resistance $R_{{\rm sp}}$, and a distributed contact resistance, $R_{\rm con}$.

Fig. 10. (a) The parasitic source/drain resistances considered in BSIM-CMG. The dashed box shows the fin; the fin is enlarged with an epitaxial grown, heavily doped layer. (b) The distributed network for the contact resistance $R_{\rm con}$; $\rho_{\rm rsd}$ is the bulk resistivity and $\rho_{{\rm c}}$ is the specific contact resistivity in the units of $\Omega-{\rm cm}^{2}$.

The contact resistance has contributions from the raised source/drain bulk resistance, ${\Delta}R_{s}$, and silicon/silicide interface resistance, ${\Delta}R_{c}$, and it is modeled as a lumped resistance using the distributed network shown in Fig. 10(b): TeX Source $$R_{\rm con}=\rho_{\rm rsd}\cdot{{L_{T}}\over{A_{\rm rsd}}}{\rm.coth}\left(\alpha\right)\eqno{\hbox{(20)}}$$ where $\alpha=L_{\rm rsd}{/}L_{T}$ and $L_{T}=\sqrt{(\rho_{c}{.}A_{\rm rsd}{)/(}\rho_{\rm rsd}{.}P_{\rm rsd})}$ with the symbols defined in Fig. 10(b).

The spreading resistance is due to a phenomenon called “current crowding,” an effect which occurs when the current is squeezed as it flows from the raised drain region into the drain extension, and is spread out as it flows from the source extension into the raised source region; this results in an increase in the resistance by $R_{{\rm sp}}$. The spreading resistance is given by [64] TeX Source $$R_{sp}={{\rho_{\rm rsd}}\over{s}}\cdot\cot\left(\theta\right)\cdot\left({{1}\over{\sqrt A_{\rm fin}}}-{{2}\over{\sqrt A_{\rm rsd}}}+{{\sqrt A_{\rm fin}}\over{A_{\rm rsd}}}\right)\eqno{\hbox{(21)}}$$ where $s$ is the shape parameter, equal to 2 for square and 1.77 for circular cross sections, $A_{\rm fin}=T_{\rm fin}\times H_{\rm fin}$, and $\theta=55^{\circ}$ for the best match with 2-D numerical device simulators.

The extension region contributes the most to the series resistance. The fringe field from the gate can cause surface accumulation at the interfaces of the extension region and the gate oxide/offset spacer; this modulates the resistivity of the region and makes $R_{\rm ext}$ bias-dependent. In BSIM-CMG, $R_{\rm ext}$ is modeled as a resistance network with two bias-independent resistances $R_{\rm ext1}$ and $R_{\rm ext2}$, and a bias-dependent resistance $R_{\rm acc}$, as shown in Fig. 10(a). Since the exact extension doping profile is often unknown, analytical expressions with fitting parameters are used to find the values of the resistances [64].

### C. Model Validation

Fig. 11 shows the output characteristics of long-channel $p$- and $n$-type FinFETs along with simulation results from the BSIM-CMG model. The basic model in BSIM-CMG predicts the silicon data accurately without the use of tuning parameters. As the device dimensions shrink, the real-device submodels, such as SCEs, mobility degradation, current saturation, and channel length modulation, start augmenting the basic model; this results in excellent scalability in all regions of operation both for $p$- and $n$-type devices (see Figs. 12 16).

Fig. 11. The drain current as a function of the drain voltage for long-channel $(L_{\rm eff}=10\mu {\rm m})$ (a) $n$-type and (b) $p$-type FinFETs. Symbols: Data, Lines: The BSIM-CMG model. The basic model in BSIM-CMG predicts the long-channel silicon data accurately without the use of tuning parameters.
Fig. 12. The drain current as a function of the gate voltage for (a) an $n$-type FinFET in linear region $(V_{{\rm ds}}=0.05 {\rm V})$, and (b) a $p$-type FinFET in saturation region $(V_{{\rm ds}}=-1.0 {\rm V})$. The channel length $L_{\rm eff}$ varies from 30 nm to 10 $\mu{\rm m}$. Symbols: Data, Lines: The BSIM-CMG model. The RMS error is about 1%.
Fig. 13. The drain current as a function of the drain voltage for (a) $n$-type and (b) $p$-type FinFETs. The channel length is equal to 30 nm and the gate voltage varies from 0 V to 1.0 V $(-{1.0} {\rm V})$. Symbols: Data, Lines: The BSIM-CMG model. The RMS error is about 1%.
Fig. 14. The transconductance $g_{m}$ as a function of the gate voltage for (a) an $n$-type FinFET in linear region, and (b) a $p$-type FinFET in saturation region. The channel length $L_{\rm eff}$ varies from 30 nm to 10 $\mu{\rm m}$. Symbols: Data, Lines: The BSIM-CMG model. The RMS error is about 1%.
Fig. 15. The outputresistance as functions of the drain voltage for (a) an $n$-type FinFET and (b) a $p$-type FinFET. The channel length is equal to 30 nm and the gate voltage varies from 0 V to 1.0 V $(-{1.0} {\rm V})$. Symbols: Data, Lines: The BSIM-CMG model. An excellent agreement was achieved.
Fig. 16. The higher-order derivatives $g_{m}$ in Fig. 14(a) with respect to the gate voltage; (a) first-derivative and (b) second-derivative. An accurate prediction of the higher-order derivatives of $g_{m}$ by BSIM-CMG enables better modeling of linearity in RF FinFETs.

In addition to the transconductance $g_{m}$ (Fig. 14) and outputresistance $1/g_{{\rm ds}}$ (Fig. 15) which together determine the ac voltage gain, an accurate prediction of the higher-order derivatives of $g_{m}$ (such that shown in Fig. 16) through mobility and current saturation submodels has an important role in RF design and enables better prediction of linearity in RF FinFETs [see Fig. 17].

Fig. 17. Analog/RF design pertinent quality assurance test results of BSIM-CMG. The model passes the McAndrew-Gummel symmetry test [53] showing excellent continuity even for higher-order derivatives of (a) drain current and (b) capacitances. (c) Harmonic balance simulation results showing response to a single tone excitation. The harmonic content of the drain current shows correct slopes up to 5th order harmonics in a plot against input power.

Fig. 18 shows the transfer characteristics of an $n$-type FinFET for different temperatures. By increasing the temperature, the silicon data show lower ON currents due to mobility degradation and higher OFF currents due to ${\rm V}_{{\rm th}}$ decrease. As the figure suggests, the model is very successful in predicting the correct temperature dependencies.

Fig. 18. (a) The drain current as a function of the gate voltage for an n-type FinFET; (a) linear scale, (b) log-scale. The channel length is equal to 60 nm and the temperature varies from $-{50} {\rm C}$ to 200 C. Symbols: Data, Lines: The BSIM-CMG model. The BSIM-CMG model is very successful in predicting the correct temperature dependencies.
SECTION IV

## BSIM-IMG MODEL

BSIM-IMG is a surface potential-based compact model targeted for UTB-SOI MOSFETs and holds potential to model emerging devices such as graphene nanoribbon transistors [11] or MoS2/WSe2 [12], [40] based devices. Many of the real-device effects are borrowed from the BSIM-CMG model with appropriate changes for independent gate operation. As a result, only a description of the basic model will be provided in this section.

### A. Basic Model: Poisson-Carrier Transport

In BSIM-IMG, the basic model solves Poisson's equation for a long-channel, independent double-gate transistor to obtain the surface potential and inversion charge at each gate. The drain current equation is derived based on the drift/diffusion equation.

#### 1) Electrostatics

Fig. 19 shows a cross-sectional view of the channel of a planar, independent double-gate transistor. Assuming GCA, Boltzmann's distribution, an undoped channel, and considering only the dominant mobile carriers, Poisson's equation is written as: TeX Source $$\partial^{2}\psi(x,y{)/}\partial x^{2}={{qn_{i}}\over{\varepsilon_{{\rm ch}}}}e^{\left({{\psi\left(x,y\right)-V_{{\rm ch}}\left(y\right)}\over{V_{{\rm tm}}}}\right)}\eqno{\hbox{(22)}}$$ where $\varepsilon_{{\rm ch}}$ is the dielectric constant of the channel. Integrating (22) across the body along the $x$ axis results in TeX Source $${\xi}_{\rm s1}^{2}-{\xi}_{\rm s2}^{2}={{{2}qn_{i}V_{{\rm tm}}}\over{\varepsilon_{{\rm ch}}}}\left[e^{\left({{\psi_{\rm s1}-V_{{\rm ch}}}\over{V_{{\rm tm}}}}\right)}-e^{\left({{\psi_{\rm s2}-V_{{\rm ch}}}\over{V_{{\rm tm}}}}\right)}\right]\eqno{\hbox{(23)}}$$ where ${\xi}_{\rm s1}$ and ${\xi}_{\rm s2}$ are the surface electric fields at the front and back gates, respectively, and $\psi_{\rm s1}$ and $\psi_{\rm s2}$ are the front and back surface potentials, respectively.

Fig. 19. Cross-sectional view of the channel region for a planar independent double-gate transistor.

Using the continuity of the electric field at the two gate-oxide interfaces, we can write TeX Source $$\xi_{\rm s1}=C_{\rm ox1}(V_{\rm fg}-V_{\rm fb1}-\psi_{\rm s1})/\varepsilon_{{\rm ch}}\eqno{\hbox{(24)}}$$ and TeX Source $${\xi}_{\rm s2}=C_{\rm ox2}(V_{\rm bg}-V_{\rm fb2}-\psi_{\rm s2}{)/}\varepsilon_{{\rm ch}}\eqno{\hbox{(25)}}$$ where the symbols are as follows: $V_{\rm fg}$ and $V_{\rm bg}$ are the front and back gate voltages; $V_{\rm fb1}$ and $V_{\rm fb2}$ are the flat-band voltages for the front and back gates, respectively; $C_{\rm ox1}$ and $C_{\rm ox2}$ are the front and back gate oxide capacitances given by $\varepsilon_{\rm ox1}{/}T_{\rm ox1}$ and $\varepsilon_{\rm ox2}{/}T_{\rm ox2}$, respectively, where $\varepsilon_{\rm ox1}$ and $\varepsilon_{\rm ox2}$ are the front and back oxide dielectrics and $T_{\rm ox1}$ and $T_{\rm ox2}$ are the front and back oxide thicknesses.

To solve the implicit (23) with two inter-dependent unknowns, $\psi_{\rm s1}$ and $\psi_{\rm s2}$, the back surface is approximated to be always in weak inversion. Using the equation for the potential of a capacitive divider node held between the two potentials $\psi_{\rm s1}$ and $V_{\rm bg}$, we can write TeX Source $$\psi_{\rm s2}=\alpha_{{\rm ch}}\psi_{\rm s1}+\alpha_{\rm ox}\left(V_{\rm bg}-V_{\rm fb2}\right)\eqno{\hbox{(26)}}$$ where $\alpha_{{\rm ch}}=C_{{\rm ch}}{/(}{\rm C}_{{\rm ch}}+C_{\rm ox2})$; $\alpha_{\rm ox}=C_{\rm ox2}{/(}{\rm C}_{{\rm ch}}{\rm+}C_{\rm ox2})$; $C_{{\rm ch}}=\varepsilon_{{\rm ch}}{/}T_{{\rm ch}}$, with $T_{{\rm ch}}$ being the channel thickness.

Substituting (26) in (23), the implicit SPE for the BSIM-IMG basic model is obtained: TeX Source \eqalignno{f\equiv &\,\left[{{C_{\rm ox1}\left(V_{\rm fg}-V_{\rm fb1}-\psi_{\rm s1}\right)}\over{\varepsilon_{{\rm ch}}}}\right]^{2}-\left[{{V_{\rm bg}-V_{\rm fb2}-\psi_{\rm s1}}\over{T_{{\rm ch}}{\rm+}\left({{\varepsilon_{{\rm ch}}}\over{\varepsilon_{\rm ox}}}\right)T_{\rm ox2}}}\right]^{2}\cr & -{{{2}qn_{i}V_{{\rm tm}}}\over{\varepsilon_{{\rm ch}}}}e^{\left({{\psi_{\rm s1}-V_{{\rm ch}}}\over{V_{{\rm tm}}}}\right)}\cr & +{{{2}qn_{i}V_{{\rm tm}}}\over{\varepsilon_{{\rm ch}}}}e^{\left({{{\alpha_{{\rm ch}}\psi}_{\rm s1}{\rm+}\alpha_{\rm ox}\left(V_{\rm bg}-V_{\rm fb2}\right)-V_{{\rm ch}}}\over{V_{{\rm tm}}}}\right)}=0.&{\hbox{(27)}}} The SPE in (27) is solved using Householder's method to obtain the front surface potential and electric field, $\phi_{\rm s1}$ and $\xi_{\rm s1}$, for the source end (by setting $V_{{\rm ch}}=V_{s}$) [65]. The front surface potential and electric field, $\phi_{\rm d1}$ and $\xi_{\rm d1}$, are also found for the drain end (by setting $V_{{\rm ch}}=V_{d}$). The corresponding back gate surface potentials $\phi_{\rm s2}$ and $\phi_{\rm d2}$ and electric fields $\xi_{\rm s2}$ and $\xi_{\rm d2}$ are then computed from (26) and (25), respectively. Finally, from Gauss's law, the inversion charge is given by TeX Source $$Q_{{\rm inv}}=\varepsilon_{{\rm ch}}\left({\xi}_{\rm s1}-{\xi}_{\rm s2}\right).\eqno{\hbox{(28)}}$$

#### 2) Transport

The drain current for a long-channel UTB transistor in BSIM-IMG is derived based on drift-diffusion transport. The equation for the drain current is given by (11). Integrating both sides of (11), and considering the fact that under quasi-static operation $I_{{\rm ds}}$ is constant along the channel, it is possible to express (11) in its integral form: TeX Source $$I_{{\rm ds}}={{W}\over{L}}\mu\left(T\right)\int_{0}^{L}{Q_{{\rm inv}}{\rm (}y)}\left[{{dV_{{\rm ch}}(y)}\over{dy}}\right].\eqno{\hbox{(29)}}$$

A simplified form of the SPE, TeX Source $${\xi}_{\rm s1}^{2}-{\xi}_{\rm s2}^{2}={{{2}qn_{i}V_{{\rm tm}}}\over{\varepsilon_{{\rm ch}}}}\left[e^{\left({{\psi_{\rm s1}-V_{{\rm ch}}}\over{V_{{\rm tm}}}}\right)}\right]\eqno{\hbox{(30)}}$$ is used to compute the drain current, as follows:

1. Solving for ${\xi}_{\rm s1}$ in (30) and using it in (28), we can write: TeX Source \eqalignno{Q_{inv}\left(y\right)=&\,\sqrt{{2}qN_{c}V_{tm}\varepsilon_{si}\left[\exp\left({{{\psi}_{\rm s1}-V_{ch}}\over{V_{tm}}}\right)\right]+\left(\varepsilon_{si}\xi_{\rm s2}\right)^{2}-}\cr &\quad\varepsilon_{si}\xi_{\rm s2}.&{\hbox{(31)}}}
2. Taking the derivatives of both side of (31) with respect to $y$, it is possible to write: TeX Source $$Q_{inv}(y){{dV_{ch}(y)}\over{dy}}=Q_{inv}(y){{d{\psi}_{\rm s1}\left(y\right)}\over{dy}}-\eta V_{tm}{{dQ_{inv}(y)}\over{dy}}\eqno{\hbox{(32)}}$$ where TeX Source $$\eta=2-{{{2}\varepsilon_{si}\xi_{\rm s2}\left(y\right)}\over{Q_{inv}\left(y\right){\rm+2}\varepsilon_{si}\xi_{\rm s2}\left(y\right)}}.\eqno{\hbox{(33)}}$$ Here, $\eta$ varies from 1 to 2 going from sub-threshold to strong inversion and is a function of $y$. To simplify the integral in (29), $\eta$ can be approximated to be independent of position, thus replacing $Q_{{\rm inv}}\left(y\right)$ and $\xi_{\rm s2}{\rm (}y)$ by their average values at source and drain ends.
3. Evaluating the integral in (29) using (32), leads to the following basic equation for $I_{{\rm ds}}$: TeX Source \eqalignno{I_{ds}=&\,\mu\left(T\right){{W}\over{L}}\Bigg[{{Q_{inv,s+}Q_{inv{\rm,}d}}\over{2}}\left({\psi}_{\rm s1,d}-{\psi}_{\rm s1,s}\right)\cr &\qquad\qquad\quad+\eta V_{tm}(Q_{inv,s}-Q_{inv{\rm,}d})\Bigg].&{\hbox{(34)}}}

### B. Model Validation

A great agreement between data for a long-channel UTBB MOSFET and simulation results from the BSIM-IMG model for transfer characteristics (Fig. 20(a)), $g_{m}$ (Fig. 20(b)), output characteristics (Fig. 21(a)), and $g_{{\rm ds}}$ (Fig. 21(b)) validate the developed physics-based basic model. In addition, excellent matching between model and measurements for the short-channel transfer characteristics and $g_{m}$ (Fig. 22), output characteristics (Fig. 23(a)), and $g_{{\rm ds}}$ (Fig. 23(b)) demonstrate the functionality of the incorporated real-device submodels in BSIM-IMG. In addition, BSIM-IMG passes a wide range of physical scalability tests [66].

Fig. 20. (a) The drain current and (b) transconductance as functions of the front gate voltage for a long-channel, $n$-type UTBB MOSFET. The drain voltage is held fixed at 0.05 V (linear region) and $V_{\rm bg}=0$, $-{0.2}$, and $-{0.5} {\rm V}$. The device has the following properties: $T_{\rm ox1}=1.2 {\rm nm}$, $T_{{\rm si}}=8 {\rm nm}$, $T_{\rm ox2}=10 {\rm nm}$, $W=10 \mu{\rm m}$, and $L=11 \mu{\rm m}$. Symbols: Data, Lines: The BSIM-IMG model. The RMS error is less 1%.
Fig. 21. (a) The drain current and (b) outputconductance as functions of the drain voltage for the device specified in Fig. 20. The front gate voltage varies from 0.5 V to 1.1 V. Symbols: Data, Lines: The BSIM-IMG model. The RMS error is less 1%.
Fig. 22. The drain current and transconductance as functions of the front gate voltage for a short-channel, $n$-type UTBB MOSFET. The drain voltage is held fixed at 0.05 V (linear region) and $V_{\rm bg}=0$, $-{0.2}$, and $-{0.5} {\rm V}$. The device has the following properties: $T_{\rm ox1}=1.2 {\rm nm}$, $T_{{\rm si}}=8 {\rm nm}$, $T_{\rm ox2}=10 {\rm nm}$, $W=10 \mu{\rm m}$, and $L=30 {\rm nm}$. Symbols: Data, Lines: The BSIM-IMG model. The RMS error is less 1%.
Fig. 23. (a) The drain current and (b) outputconductance as functions of the drain voltage for the device specified in Fig. 22. The front gate voltage varies from 0.5 V to 1.1 V. Symbols: Data, Lines: The BSIM-IMG model. An excellent agreement between the data and simulation results was achieved.
SECTION V

## CONCLUSION

The BSIM Group has developed physics-based, computationally efficient, and accurate compact models, BSIM-CMG and BSIM-IMG, for the FinFET and UTB transistor. The models are surface potential-based and incorporate real-device submodels with appropriate physics and technology related parameters to support devices from different manufacturers and technologies, for digital logic, analog, and RF IC designs. Not discussed in this paper is a robust C-V model included in both BSIM-CMG and BSIM-IMG to precisely simulate the transcapacitances.

The BSIM-CMG and BSIM-IMG models:

1. capture the important physics of thin body multi-gate transistors such as the “volume inversion” and the “dynamic $V_{{\rm th}}$ shift” for body bias in UTBB transistors;
2. pass all the quality tests for compact models including the McAndrew-Gummel and ac source-drain symmetry tests [53], slope ratio test [67], and physical scalability tests;
3. perform an excellent job of matching to silicon hardware data because of their robust basic models and complete and advanced real-device submodels. The group also benefits from many industry collaborators for feedback towards model improvement.

As long as the transistors work as a barrier-controlled device (which is built into the models) and the fundamental physics of the operation does not break, the models can be improved to remain accurate. In fact, the predictive model files for BSIM-CMG for 10-nm and 7-nm nodes are currently available [68], which allows design explorations to start even before the technology is ready. In addition, both models hold potential for alternative transistors: monolayer transistors like graphene nanoribbon, WSe2, and MoS2 can be modeled with BSIM-IMG, whereas, BSIM-CMG can be used to model carbon-nanotube and nanowire FETs. The BSIM-CMG model is open to public [69]. In addition to extensive industry users (from both digital and analog/RF communities), many researchers and students around the world are also using it to design and study circuit building blocks for future technology nodes. The BSIM-IMG model is under standardization by CMC.

It is also worth mentioning that in the BSIM Group, a great focus is now on reducing the simulation time even more (without losing the accuracy) to enable even larger circuit design optimization and predictive statistical process variability assessment.

### ACKNOWLEDGMENT

The authors would like to thank all members of the industry who helped us with prompt feedback during the model development cycle, and Kyle Holland of the University of Alberta, Edmonton, AB, Canada for helpful comments on the content of the paper.

## Footnotes

This work was supported in part by Semiconductor Research Corporation (SRC Task 1135, 1149, 1451 and 2055), IC Manufacturers (TSMC, IBM, GLOBALFOUNDRIES, Intel), fabless companies (Qualcomm), EDA vendors (Synopsys, Cadence, Mentor Graphics), and the Compact Model Council.

Navid Paydavosi, Sriramkumar Venugopalan, Juan Pablo Duarte, Srivatsava Jandhyala, Ali M. Niknejad and Chenming Calvin Hu are with the Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720, USA and also Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India Corresponding author: N. Paydavosi (navidp@ece.berkeley.edu)

Yogesh Singh Chauhan was with the Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720, USA

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

1The term “FinFET,” throughout this paper, refers to both a fin-based device architecture (e.g., in this sentence) and a fin-based field-effect transistor (e.g., in the first sentence of the next paragraph).

2BSIM stands for Berkeley short-channel, insulated-gate, field-effect transistor model.

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