A memory efficient IPv6 lookup engine on FPGA

High-speed IP lookup remains a challenging problem in next generation routers due to the ever increasing line rate and routing table size. The evolution towards IPv6 results in long prefix length, sparse prefix distribution, and potentially very large routing tables. In this paper we propose a memory-efficient IPv6 lookup engine on Field Programmable Gate Array (FPGA). Static data structures are employed to reduce the on chip memory requirement. We design two novel techniques: implicit match identification and implicit match relay, to enhance the overall memory efficiency. Our experimental results show that the proposed techniques reduce memory usage by 30%. Using our architecture, state-of-the-art FPGA devices can support 2 copies of IPv6 routing table containing around 330k routing prefixes. Using dual ported BRAM and external SRAM, 4 pipelines can be implemented on a single device, achieving a throughput of 720 million lookups per second (MLPS).