Modeling of Charge-Trapping/Detrapping-Induced Voltage Instability in High- $k$ Gate Dielectrics

Investigation of trapping-/detrapping-induced voltage instabilities does demand not only accurate measurements but also a precise methodology for extracting the exact magnitude of the voltage shifts in the hysteresis curves which is indispensable. Particularly, in dc measurements where the induced voltage shifts are small, an excellent accuracy of the analysis method is required. Therefore, in this paper, we develop a new methodology that, with excellent agreement, models the complete measured
$I_{d}$
–
$V_{g}$
hysteresis curves using least squares support vector machines. Furthermore, we apply this model and formulate an optimization problem resulting in the maximum trap-induced voltage shifts in the entire hysteresis curves. Also, for the first time, we quantify the induced error on these extracted maxima. Finally, we illustrate the applicability of the introduced methodology by profiling the initially present and stress-induced defects in a 1-nm
$\hbox{SiO}_{2}$
/3-nm HfSiO dielectric stack.