DSP power reduction through Generalized Carry-Save arithmetic

We present a new method to systematically parallelize networks of additions and multiplications to dramatically reduce power dissipation in digital signal processing (DSP) blocks. This new method is termed Generalized Carry-Save (GCS) arithmetic. Results are presented for three industrial DSP blocks, separately implemented in IBM 130 nm, TI 65 nm and TI 45 nm technologies. Compared with the best delays obtainable using the best scripts from the leading commercial synthesis tool, GCS produces DSP block implementations that are at least 30% and up to 2X faster for similar area. As a consequence, the power supply voltage can be reduced to realize quadratic power savings for the same delays.