Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging

In this study, a flexible wafer level packaging (FWLP) having the capability of redistributing the electrical circuit is proposed to resolve the problem of assembling a fine-pitched chip to a coarse-pitched substrate. In the FWLP, the diced chip is picked and back-sided attached to the flexible substrate after the functional testing. Besides, the solder on rubber (SOR) design is applied to expand the chip area and also to provide a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. The design concepts as well as the fabrication processes for the fan-out type FWLP would be described herein. In our previous research, it was shown the reliability of FWLP could easily pass 1300 cycles thermal cycling test (JEDEC condition G, $-40^{\circ}{\rm C}\sim 125^{\circ}{\rm C}$). Besides, the failure mode was moved from solders to copper trace lines. Therefore, the packaging level reliability of the copper trace structure of FWLP is investigated and discussed in this research. The $2^{5}$ factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information of the packaging. Through the reliability assessment and constrained optimization technology, the fan-out FWLP could be further improved within the target range of design parameters. The FWLP structure proposed in this research can be redesigned to have the double-sided I/O capability, and will have a high potential for various advanced packaging applications.