A PVT aware accurate statistical logic library for high-κ metal-gate nano-CMOS

The semiconductor industry is headed towards a new era of scaling and uncertainty with new key building blocks for the next-generation chips, the high-kappa metal-gate transistor. There is a need for statistical characterization of high-kappa metal-gate digital gates as a function of process parameter variations to make them available for designers. In this paper, we present a methodology for PVT aware high-kappa metal-gate logic library creation while considering the variability effect in 15 parameters. First, statistical models for GIDL current (I circ
_GIDL
), offcurrent (I circ
_off
) and drive current (I circ
_ON
) are presented at the device level. This is followed by statistical characterization of logic cells at roomtemperature. Data for subthreshold current (I circ
_sub
), I circ
_GIDL
, dynamic current (I circ
_dyn
) and delay is presented. This is followed by results for PVT aware characterization of logic cells. To the best of the authors' knowledge, this is the first research which provides a PVT aware statistical characterization for high-kappa metal-gate nano-CMOS based logic gates.