QSYN: Queueing networks synthesis for system on chip

Queueing networks represent a powerful model of computation (MOC) with strong theoretical foundations and a wide range of applications. Design productivity for system on chip (SOC) requires increasing the level of abstraction for the design of SOC. However, achieving better productivity through raising the level of abstraction can only be obtained with the help of automatic MOC transformation techniques. In this paper, we propose QSYN a tool for the automatic transformation of queueing network based MOC to an executable platform on FPGA. Case studies demonstrate the validity of our approach.