Session 2: Process technology — high-k metal-gate integration

There are six papers in this session on the integration of high-k/metal gates in a CMOS flow. High-k metal gate stacks have now been introduced in production for the 45nm node. Work function setting and control are still critical and will need further improvement and understanding in order to continue scaling the threshold voltage as well as fabrication of multi Vt devices using high-k metal gate stacks. This session includes an invited paper that describes chemical mechanical polishing as a critical technology enabler for the integration of metal gate electrodes with high-k materials in a gate last flow and several papers on work function control and setting using various approaches. The contributed papers provide basic understanding on the effects of various metal oxides on the SiO
2
/high-k interface, EOT scaling and work function control.