Modeling the Drain Current of DG FD SOI NMOS Devices with N+/P+ Poly Top/Bottom Gate

This paper reports an analytical drain current model of double-gate (DG) fully-depleted (FD) SOI NMOS devices with the n
⁺
/p
⁺
poly top/ bottom gate considering the threshold/ transition voltage effects. Via a comprehensive current conduction mechanism model, the analytical drain current model considering the threshold/transition voltage effects could provide an accurate prediction of performance the 100 nm DG FD SOI NMOS device with the n
⁺
/p
⁺
poly top/bottom gate as verified by the 2D simulation results.