Rapid estimation of control delay from high-level specifications

We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesized behavioral design goes through both the data path and the control logic; yet most scheduling algorithms account only for data path and ignore control delay, leading to timing uncertainties in the resulting designs. We present an estimation technique for computing a fast, robust, scalable, and reasonably accurate approximation of the control delay from behavioral specifications. The delay estimate is formulated in terms of the properties of the input specification and other inputs to the synthesis process such as resource constraints.