A fully physical model for leakage distribution under process variations in nanoscale double-gate CMOS

Double-gate CMOS is projected to replace classical bulk and SOI technologies around the 32nm node. Predicting the impact of process variations on yield for these novel devices is necessary at an early stage of the design cycle, to enable optimal technology and circuit design choices. This paper presents a fully physical model for double-gate leakage distribution due to gate length (L) and body thickness (t/sub si/) variations, both for single devices and stacks. The model is derived directly from the solution of Poisson's and Schrodinger's equations, and thus captures the effect of unique double-gate phenomena such as volume inversion and quantum confinement. It is scalable to L = 13nm and t/sub si/ = 3nm, with less than 2% error for 3/spl sigma/ variation as large as 20% of nominal process parameters.