A CPPLL hierarchical optimization methodology considering jitter, power and locking time

In this paper, a hierarchical optimization methodology for charge pump phase-locked loops (CPPLLs) is proposed. It has the following features: 1) A comprehensive and efficient behavioral modeling of the PLL enables fast simulations and includes the important PLL performances jitter, power and locking time, as well as stability constraints for the nonlinear locking process and the linear lock-in state; 2) Behavioral modeling of the PLL building blocks addresses as behavioral-level parameters: current and jitter of the charge pump (CP), gain, current and jitter of the voltage controlled oscillator (VCO), as well as R, C's of the loop filter (LF). It enables a proper propagation of PLL specifications down to the circuit-level design parameters; 3) An accurate and efficient performance space exploration technique on circuit level provides the feasible regions of the behavioral-level parameters of the building block by multidimensional Pareto-optimal fronts. This enables a first-time-successful top-down optimization process. Experimental results show the efficacy and efficiency of the presented method. The methodology can be applied to other large-scale analog circuits