Design of a robust 8-bit microprocessor to soft errors

This work presents a fault-tolerant version of the mass-produced 8-bit microprocessor M68HC11. It is able to tolerate single event transients (SETs) and single event upsets (SEUs). Based on triple modular redundancy (TMR) and time redundancy (TR) fault tolerance techniques, a protection scheme was implemented at high level in the sensitive areas of the microprocessor by using only standard gates in order to save design time. Furthermore, fault-tolerant IC design issues and results in area and performance were compared with a non-protected microprocessor version