FPGA-based customizable systolic architecture for image processing applications

The present work focuses on the development of a reconfigurable systolic-based architecture for low-level image processing. The architecture is customizable providing the possibility to perform window operations for masks of 3 times3, 5 times5 and 7 times7 coefficients. A 2D systolic array of processing elements have been implemented, based on parallel modules with internal pipeline operation where every processing element can be configured according to a control word. In addition the array is provided with a group of image buffers to reduce the number of access to data memory and to extend the array capabilities allowing the possibility of chaining interconnection of multiple processing blocks. Every buffer constitutes a repository of data that can be reused for different processing blocks. Preliminary results using 640 times 480 gray level images show that window-based operations can be performed in real time, processing an image frame in 5 ms, achieving a throughput of around 3.6 GOPS