Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application

We proposed "reverse-order source/drain formation with double offset spacer" (RODOS) structure for low-power and high-speed applications. Both simulation and experimental data were used to evaluate the potential of the structure. It showed improved performance in terms of poly-depletion effect, dc characteristics, gate delay (CV/I), switching energy (CV/sup 2/) and linearity (V/sub IP3/). It satisfied all the requirements of LOP and LSTP for 90 nm technology node in ITRS 2002. Simulation predicted 794 /spl mu/A//spl mu/m in on-current, 0.1 nA//spl mu/m in off-current, 65 mV/V in DIBL, 80 mV/dec in SS, 1.29 ps in gate delay, 198 GHz in f/sub T/ and 0.151 fJ in switching energy in addition to enhanced linearity. Finally, we confirmed the high feasibility and potential of the RODOS MOSFET's for low-power and high-speed applications such as an LNA in portable communication appliances.