# IEEE Transactions on Circuits and Systems I: Regular Papers

## Volume 65 Issue 9 • Sept. 2018

The purchase and pricing options for this item are unavailable. Select items are only available as part of a subscription package. You may try again later or contact us for more information.

## Filter Results

Displaying Results 1 - 25 of 47

Publication Year: 2018, Page(s):C1 - C4
| PDF (178 KB)
• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2018, Page(s): C2
| PDF (111 KB)
• ### A Low-Power, Wireless, Capacitive Sensing Frontend Based on a Self-Oscillating Inductive Link

Publication Year: 2018, Page(s):2645 - 2656
| | PDF (3512 KB) | HTML

Wireless sensing systems are becoming popular in a range of applications, particularly in the case of biomedical circuits and food monitoring systems. A typical wireless sensing system, however, may require considerable complexity to perform the necessary analog to digital conversion and subsequent wireless transmission. Alternatively, in the case of inductive link based systems, large, manually o... View full abstract»

• ### A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS

Publication Year: 2018, Page(s):2657 - 2668
| | PDF (3024 KB) | HTML

This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA's output matching network, the inductance ratio should be equal to the load/source resistance ratio to achieve broadband impedance transformation... View full abstract»

• ### A 7-GHz CMOS Bidirectional Variable Gain Amplifier With Low Gain and Phase Imbalances

Publication Year: 2018, Page(s):2669 - 2678
| | PDF (3644 KB) | HTML

This paper presents a bidirectional variable gain amplifier (BVGA) with a low imbalance between amplification directions in 65-nm CMOS process. The BVGA is composed of two symmetric bidirectional amplifiers (BA) and a distributed attenuator (DA) for a low directional imbalance. The amplification direction is changed by the switching supply and ground voltages of a common gate amplifier in the BA. ... View full abstract»

• ### A$K\text{-}/Ka$-Band Concurrent Dual-Band Single-Ended Input to Differential Output Low-Noise Amplifier Employing a Novel Transformer Feedback Dual-Band Load

Publication Year: 2018, Page(s):2679 - 2690
| | PDF (3764 KB) | HTML

A concurrent dual-band single-ended input to differential output (single-ended-to-differential) low-noise amplifier (LNA) employing a novel transformer feedback single-ended to-differential dual-band load is proposed. The developed LNA topology is flexible in controlling the stopband notch frequency by optimizing the transformer's self-inductance and coupling coefficient. It also has a unique adva... View full abstract»

• ### A 2.5–5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection

Publication Year: 2018, Page(s):2691 - 2702
Cited by:  Papers (1)
| | PDF (3657 KB) | HTML

A 2.5-5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs) require additional circuitry for resolving a phase alignment mismatch between the PLL loop and injection path, the presented ILPLL exhibits a simplif... View full abstract»

• ### Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters

Publication Year: 2018, Page(s):2703 - 2714
| | PDF (2788 KB) | HTML

This paper demonstrates a completely on-chip implementation of expansion and compression of continuous-time, wideband, analog pulses. The input pulse is fed to a continuous-time filter whose delay exceeds the pulse duration. Once the pulse is completely inside the filter, it is stored in the form of the filter's state-variables, which can completely reconstruct the pulse. Instantaneously decreasin... View full abstract»

• ### Wideband Techniques for Outphasing Power Amplifiers

Publication Year: 2018, Page(s):2715 - 2725
| | PDF (2049 KB) | HTML

In this paper a wideband, high-power amplifier that achieves an output power of 20 W with a bandwidth greater than one octave in the L and S bands is presented. Two ~10 W Class AB PAs are implemented with Gallium Nitride-high electron mobility transistor devices and a low loaded-Q matching network to achieve wideband performance. High power added efficiency (PAE) is achieved by combining outphased... View full abstract»

• ### Design and Hardware Implementation of Neuromorphic Systems With RRAM Synapses and Threshold-Controlled Neurons for Pattern Recognition

Publication Year: 2018, Page(s):2726 - 2738
| | PDF (9566 KB) | HTML

In this paper, a hardware-realized neuromorphic system for pattern recognition is presented. The system directly captures images from the environment, and then conducts classification using a single layer neural network. Metal-oxide resistive random access memory (RRAM) is used as electronic synapses, and threshold-controlled neurons are proposed as postsynaptic neurons to save the system area and... View full abstract»

• ### Hardware Implementation of an Event-Based Message Passing Graphical Model Network

Publication Year: 2018, Page(s):2739 - 2752
| | PDF (3974 KB) | HTML

This paper presents a hardware system that implements a factor graph, where messages are sent using an event-based belief propagation algorithm. The system, comprising an FPGA and an application specific integrated circuit (ASIC) chip, can be used to construct a graph with upto 16 output message channels. The ASIC chip with 16 channels is fabricated in a 0.35 um 2P4M CMOS process and occupies 2.16... View full abstract»

• ### A CMOS Follower-Type Voltage Regulator With a Distributed-Element Fractional-Order Control

Publication Year: 2018, Page(s):2753 - 2763
| | PDF (7598 KB) | HTML

This paper presents an application of a fractional-order control in an on-chip follower-type 1.8 V/100 mA voltage regulator to achieve a good stability with any load capacitance. The controller approximates an integrator with the fractional order of 0.5, whose phase lag is not more than 45°. The fractional order is set by the fractional-order impedance of the resistive p-type MOS capacitor (R-PMOS... View full abstract»

• ### A Digitally Interfaced Analog Correlation Filter System for Object Tracking Applications

Publication Year: 2018, Page(s):2764 - 2773
| | PDF (3687 KB) | HTML

This paper reports a 24 × 57 correlation filter system for object tracking applications. While digital interfacing of the input and output data enabled a standard and flexible way of communication with pre- and post-processing digital blocks, the multiply-accumulate (MAC) operations were performed in the analog domain to save power and area. The proposed system utilizes non-volatile floating-gate ... View full abstract»

• ### A Subthreshold Buffer-Based Biquadratic Cell and its Application to Biopotential Filter Design

Publication Year: 2018, Page(s):2774 - 2783
| | PDF (2762 KB) | HTML

This paper develops a compact power-efficient CMOS buffer to operate as a nanopower lowpass biquadratic cell. Unlike other recently reported CMOS biquads with passband gains that are attenuated by the bulk effect, this biquad attains a near 0-dB passband gain without gain compensation. It acquires the same levels of input and output common-mode voltages making it useful for cascade realization of ... View full abstract»

• ### A Self-Powered Supply-Sensing Biosensor Platform Using Bio Fuel Cell and Low-Voltage, Low-Cost CMOS Supply-Controlled Ring Oscillator With Inductive-Coupling Transmitter for Healthcare IoT

Publication Year: 2018, Page(s):2784 - 2796
Cited by:  Papers (2)
| | PDF (4093 KB) | HTML

This paper proposes a self-powered disposable supply-sensing biosensor platform for big-data-based healthcare applications. The proposed supply-sensing biosensor platform is based on bio fuel cells and a 0.23-V 0.25-μm zero-Vthall-digital CMOS supply-controlled ring oscillator with a current-driven pulse-interval-modulated inductive-coupling transmitter. The fully digital, and current-d... View full abstract»

• ### A High-Voltage DAC-Based Transmitter for Coded Signals in High Frequency Ultrasound Imaging Applications

Publication Year: 2018, Page(s):2797 - 2809
| | PDF (5869 KB) | HTML

An ultrasound transmitter based on a high-voltage digital-to-analog converter (HVDAC) is presented in this paper. The transmitter is implemented in a 0.25-$\mu \text{m}$high-voltage CMOS process provided by foundry, integrating the digital control circuitry and HVDAC on a single chip. By employing a fast-slewing DAC in conjunct... View full abstract»

• ### A Wirelessly Powered CMOS Electrochemical Sensing Interface With Power-Aware RF-DC Power Management

Publication Year: 2018, Page(s):2810 - 2820
Cited by:  Papers (2)
| | PDF (4325 KB) | HTML

A wirelessly powered electrochemical sensing chip with high-efficiency adaptive power management for a wide RF-powering range and a low-noise chopper-stabilization potentiostat for high-resolution electrochemical current detection is presented. The chip is fabricated using a 0.18-μm CMOS process. A novel, power-aware, multiple-path, RF-energy harvesting front end extends the high-efficiency (>2... View full abstract»

• ### A$16\times16$CMOS Amperometric Microelectrode Array for Simultaneous Electrochemical Measurements

Publication Year: 2018, Page(s):2821 - 2831
| | PDF (2494 KB) | HTML

There is a requirement for an electrochemical sensor technology capable of making multivariate measurements in environmental, healthcare, and manufacturing applications. Here, we present a new device that is highly parallelized with an excellent bandwidth. For the first time, electrochemical cross-talk for a chip-based sensor is defined and characterized. The new CMOS electrochemical sensor chip i... View full abstract»

• ### Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC

Publication Year: 2018, Page(s):2832 - 2841
Cited by:  Papers (1)
| | PDF (1823 KB) | HTML

In this paper, signal-to-noise ratio (SNR) degradation from random clock jitter in a current-steering digital-to-analog converter (CS-DAC) is analyzed based on a timing-to-amplitude error conversion method. A closed-form equation is derived to predict SNR for white noise clock jitter (WN-J) and low-pass filtered clock jitter (LPF-J) in non-return-to-zero (NRZ) and return-to-zero (RZ) DAC. Especial... View full abstract»

• ### Impedance Matching and Reradiation in LPTV Receiver Front-Ends: An Analysis Using Conversion Matrices

Publication Year: 2018, Page(s):2842 - 2855
Cited by:  Papers (2)
| | PDF (2775 KB) | HTML

Linear periodically time-varying (LPTV) circuits are finding increased prominence in reconfigurable transceiver applications. Impedance matching of such circuits to the antenna impedance is essential for fully on-chip receiver topologies. However, deriving the S11of an LPTV circuit is non-trivial in general. Moreover, reflections at harmonic offsets from input frequencies can also be ex... View full abstract»

• ### Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications

Publication Year: 2018, Page(s):2856 - 2868
| | PDF (5926 KB) | HTML

In this paper, the designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further reduce power consumption and improve performance. Non-iterative ALMs, that use three inexact mantissa adders, are presented. The proposed iterative ALMs (IALMs) use a set-one adder in both mantissa adders during an iteration; they also use lower-part-or adders and approx... View full abstract»

• ### A Low-Latency and Low-Complexity Point-Multiplication in ECC

Publication Year: 2018, Page(s):2869 - 2877
| | PDF (2082 KB) | HTML

Elliptic curve cryptography (ECC) has received attention, because it can achieve the same security level as other asymmetric methods while using a key with smaller length. Although ECC is more efficient compared with other asymmetric methods, the fast computation of ECC is always desirable. In this paper, a fixed-base comb point multiplication method has been used to perform regular point multipli... View full abstract»

• ### FIR Filter Realization via Deferred End-Around Carry Modular Addition

Publication Year: 2018, Page(s):2878 - 2888
Cited by:  Papers (1)
| | PDF (3675 KB) | HTML

Hardware realization of FIR filters that are based on residue number systems leads to increased speed and reduced power, where besides the popular Mersenne numbers, several moduli of the form 2n± δ (δ ≥ 3) are commonly used. However, additional weighted 2i(i> 1) end-around carries (EACs) slow down and complicate the required modular adders in comparison to modulo-(2... View full abstract»

• ### A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation

Publication Year: 2018, Page(s):2889 - 2902
| | PDF (3677 KB) | HTML

This paper describes a hardware-efficient feedback polynomial topology for digital predistortion (DPD) linearization of power amplifiers. Unlike the existing pruned Volterra-series DPD linearization that compensates the nonlinearities in parallel, our topology tailors a feedback memory block, such that the nonlinearities and memory effects can be constructed separately, minimizing the running comp... View full abstract»

• ### Analog Circuit Implementation of Fractional-Order Memristor: Arbitrary-Order Lattice Scaling Fracmemristor

Publication Year: 2018, Page(s):2903 - 2916
| | PDF (3049 KB) | HTML

In this paper, based on fractional calculus, the fractional-order memristor, an arbitrary-order fracmemristor, is proposed to be implemented in the form of a lattice scaling analog circuit. Since the concept of the memristor is generalized from the classic integer-order memristor to that of the fractional-order memristor, fracmemristor, it is natural to ponder a challenging theoretical problem to ... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK