# IEEE Transactions on Circuits and Systems I: Regular Papers

## Volume 65 Issue 7 • July 2018

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## Filter Results

Displaying Results 1 - 25 of 29

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2018, Page(s): C2
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• ### USER-SMILE: Ultrafast Stimulus Error Removal and Segmented Model Identification of Linearity Errors for ADC Built-in Self-Test

Publication Year: 2018, Page(s):2059 - 2069
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Linearity testing of analog-to-digital converters (ADCs) is very challenging and expensive due to the stringent linearity requirement on the stimulus and the extremely long test time. This paper introduces a novel method for ADC static linearity testing, allowing the stimulus linearity requirement to be significantly relaxed and the test time to be significantly reduced compared to the state-of-ar... View full abstract»

• ### $W$-Band (92–100 GHz) Phased-Array Receive Channel With Quadrature-Hybrid-Based Vector Modulator

Publication Year: 2018, Page(s):2070 - 2082
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This paper presents a W-band (92-100 GHz) phased array receive channel adopting a power domain vector modulator (VM), which utilizes a 90° hybrid-coupler-based phase interpolator. The quadrature hybrid leverages its inherent functions of quadrature phase splitting and power combining to interpolate phases by combining the weighted signals from variable gain amplifiers in the power domain. Compared... View full abstract»

• ### A 76–84 GHz CMOS$4\times$Subharmonic Mixer With Internal Phase Correction

Publication Year: 2018, Page(s):2083 - 2096
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A CMOS 4× subharmonic mixer (SHM) with an internal phase error correction mechanism operating at mm-wave frequencies is proposed in this paper. The SHM operates with a 81-GHz RF input signal and a 20-GHz local oscillator (LO) signal to produce a 1-GHz output. The single ended input is converted into octet-phase, through an active input balun, an active polyphase filter, and certain phase adders. A... View full abstract»

• ### A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection

Publication Year: 2018, Page(s):2097 - 2108
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When operating at a gigahertz-level frequency, a high-frequency signal is distorted and degraded through the channel. To meet the demand of low cost and the low power consumption for consumer electronic products, this paper proposes a power-saving adaptive equalizer with digital-controlled self-slope detection to compensate channel losses. Reducing and shutting down high-speed circuits in addition... View full abstract»

• ### A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

Publication Year: 2018, Page(s):2109 - 2117
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This paper presents a PLL supporting diverse low-power clocking needs including wide input (6-200 MHz) and output (0.15-5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high -3dB PLL bandwidth (&gt;40% of f<sub>REF</sub> = 19.2 MHz), and the proposed reference current generator (IrefGen) provides a... View full abstract»

• ### A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector

Publication Year: 2018, Page(s):2118 - 2126
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A high-order cascaded phase-locked loop (PLL) architecture using a sub-sampling delay-locked loop (DLL) is proposed to break the tradeoff between the loop bandwidth and the number of integrator in the feedback loop without significantly degrading the settling time or reference spur. A clock-skew-sampling phase detector is also proposed to extend the stable detection range of the sub-sampling phase... View full abstract»

• ### Low$1/f^{3}$Phase Noise Quadrature LC VCOs

Publication Year: 2018, Page(s):2127 - 2138
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Series-coupled quadrature LC voltage-controlled oscillators(SQVCOs) perform robustly over a wide tuning range, but have a higher 1/f3phase noise than their single-phase counterparts. Switching transistors inject noise into the tank only once per cycle leading to an asymmetric impulse sensitivity function(ISF) and large flicker noise upconversion. Circuit topologies with additional capac... View full abstract»

• ### A W-Band Balanced Power Amplifier Using Broadside Coupled Strip-Line Coupler in SiGe BiCMOS 0.13-$\mu\text{m}$Technology

Publication Year: 2018, Page(s):2139 - 2150
Cited by:  Papers (1)
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Load-variation insensitivity, for impedance matching between power amplifiers (PAs) and transmitting antennas, contributes to challenging the design of millimeter-wave wireless systems. In this paper, a W-band two-way balanced PA based on a compact quadrature coupler with a broadside coupled stripline (BCSL) as the core is presented to enhance the load-variation insensitivity and stability. The pr... View full abstract»

• ### A Transformer-Based 3-dB Differential Coupler

Publication Year: 2018, Page(s):2151 - 2160
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This paper presents a transformer-based 3-dB differential coupler, which features the suppression of both commonmode and cross-mode signals. Transformer is utilized rather than the quarter-/half-wavelength lines, and the circuit size can be significantly reduced. The bandwidth of the proposed differential coupler can be enhanced by increasing the coupling coefficient of the transformer. For the pr... View full abstract»

• ### An L-Band Low Phase Noise Evanescent-Mode Cavity-Based Frequency Synthesizer

Publication Year: 2018, Page(s):2161 - 2168
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In this paper, an L-band low phase noise evanescent-mode (EVA) cavity-based frequency synthesizer is developed, implemented, and experimentally validated. The oscillator is integrated on the substrate of a high-Q (Qu≥ 430) EVA resonator board to reduce parasitics in the circuit. A piezoelectric actuator is used as a tuner. A phase-locked loop is used to control the output frequency. The... View full abstract»

• ### A 1 pF-to-10 nF Generic Capacitance-to-Digital Converter Using Zero-Crossing$\Delta\Sigma$Modulation

Publication Year: 2018, Page(s):2169 - 2182
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Conventional capacitance-to-digital converters (CDCs) suffer limitations either on narrow capacitance range or low resolution for jitter-induced noise and high power consumption. In order to avoid these limitations, a 13-b 1 pF-10 nF generic CDC is presented. In the proposed CDC with the oversampled ΔΣ modulation, the zero-crossing-based circuits (ZCBCs) are used to replace the operational transco... View full abstract»

• ### Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes

Publication Year: 2018, Page(s):2183 - 2195
Cited by:  Papers (1)
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Probabilistic gradient descent bit-flipping (PGDBF) is a hard-decision decoder for low-density parity-check (LDPC) codes, which offers a significant improvement in error correction, approaching the performance of soft-information decoders on the binary symmetric channel. However, this outstanding performance is known to come with an augmentation of the decoder complexity, compared to the non-proba... View full abstract»

• ### A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry

Publication Year: 2018, Page(s):2196 - 2209
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Despite the considerable effort has been put on the application of Non-Volatile Memories (NVMs) in Field-Programmable Gate Arrays FPGAs, previously suggested designs are not mature enough to substitute the state of-the-art SRAM-based counterparts mainly due to the inefficient building blocks and/or the overhead of programming structure which can impair their potential benefits. In this paper, we p... View full abstract»

• ### A Novel Memristor-Based Circuit Implementation of Full-Function Pavlov Associative Memory Accorded With Biological Feature

Publication Year: 2018, Page(s):2210 - 2220
Cited by:  Papers (1)
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In this paper, a memristor-based Pavlov associative memory circuit accorded with the biological feature is proposed. The proposed circuit mainly consists of neuron module, synapse module with synaptic weight measurement function and feedback module. Variety of learning and forgetting functions are considered. The condition of learning is that the food neuron and ring neuron are activated simultane... View full abstract»

• ### An Algorithmic Approach for Signal Measurement Using Symbolic Dynamics of Tent Map

Publication Year: 2018, Page(s):2221 - 2231
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The symbolic time series generated by a unimodal chaotic map starting from any initial condition creates a binary sequence that contains information about the initial condition. A binary sequence of a given length generated this way has a one-to-one correspondence with a given range of the input signal. This can be used to construct analogue to digital converters (ADC). However, in actual circuit ... View full abstract»

• ### Event-Triggered Control for Consensus Problem in Multi-Agent Systems With Quantized Relative State Measurements and External Disturbance

Publication Year: 2018, Page(s):2232 - 2242
Cited by:  Papers (4)
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For decreasing communication load and overcoming network constrains, such as the limited bandwidth and data loss in multi-agent networks, this paper integrates the two control strategies to investigate the bounded consensus problem of multi-agent systems (MASs) with external disturbance on the basis of an undirected graph, namely, the quantized control and the event-triggered control. In the exist... View full abstract»

• ### Adaptive Fault-Tolerant Consensus for a Class of Uncertain Nonlinear Second-Order Multi-Agent Systems With Circuit Implementation

Publication Year: 2018, Page(s):2243 - 2255
Cited by:  Papers (1)
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In this paper, a robust fault-tolerant consensus control strategy and its circuit implementation method are proposed for a class of nonlinear second-order leader-following multi-agent systems against multiple actuator faults and time-varying state/input-dependent system uncertainties. The faults of partial loss of actuator effectiveness and bias-actuators are considered without knowing eventual fa... View full abstract»

• ### Performance Assessment of Discrete-Time Extended State Observers: Theoretical and Experimental Results

Publication Year: 2018, Page(s):2256 - 2268
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This paper evaluates the performance of the discrete-time linear extended state observer (ESO) for a disturbed nonlinear discrete-time system with uncertainties. Since the performance of the ESO is dominated by the choice of the gain parameter, the goal of this paper is to analyze the behavior of the observation error when the gain parameter varies from zero to infinity. We show that for the ESO c... View full abstract»

Publication Year: 2018, Page(s):2269 - 2278
Cited by:  Papers (1)
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A 0.88 mm<sup>2</sup> 65-nm analog-to-digital converter (ADC)-based serial link transceiver is designed with a maximum-likelihood sequence detector (MLSD) for robust equalization. The MLSD is optimized in a pipelined look-ahead architecture to reach 10 Gb/s at 5.8 pJ/b and 5 Gb/s at 3.9 pJ/b, making it practical for an energy-efficient ADC-based serial link. Compared with linear equali... View full abstract»

• ### A Dual-Resolution Wavelet-Based Energy Detection Spectrum Sensing for UWB-Based Cognitive Radios

Publication Year: 2018, Page(s):2279 - 2292
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An ultra-wideband (UWB)-based cognitive radio (CR) is a promising technique to utilize 3.1-10.6 GHz band efficiently for high data-rate short-range wireless connectivity even in the overcrowded spectrum. This paper investigates a low power wavelet-based energy detection spectrum sensor that provides high-order band-pass filter function and spectral cooperative sensing with fast spectrum sensing (S... View full abstract»

• ### Design of an On-Silicon-Interposer Passive Equalizer for Next Generation High Bandwidth Memory With Data Rate Up To 8 Gb/s

Publication Year: 2018, Page(s):2293 - 2303
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In this paper, we propose a new on-silicon-interposer passive equalizer for next generation high bandwidth memory (HBM) with 1024 I/O lines and 8-Gb/s data transmission, which is four times higher than the data rate of HBM generation 2. The proposed equalizer meets the three requirements for the implementation of ultra-high bandwidth interface with wide I/O lines: 1) small area; 2) fine pitch; and... View full abstract»

• ### A Frequency-Folded ADC Channelizer With Digital Equalization and Relaxed Anti-Alias Filtering

Publication Year: 2018, Page(s):2304 - 2317
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This paper presents a mixed-signal broadband channelizer that employs digital post-processing for reducing the analog anti-aliasing requirement in an N-path frequency-folding receiver architecture. In the approach, a signal of bandwidth Nf<sub>LO</sub>/2 is downconverted using N phases of a rectangular pulse waveform at a fundamental frequency of f<sub>LO</sub> with a duty-... View full abstract»

• ### A Cost-Effective Adaptive Rectifier for Low Power Loosely Coupled Wireless Power Transfer Systems

Publication Year: 2018, Page(s):2318 - 2329
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This paper introduces an integrated receiver circuit based on a full-wave adaptive rectifier (AR). It achieves complex impedance matching and enables complexity and cost reduction in resonant wireless power transfer (WPT) systems. The conversion and system efficiency based on this AR receiver are theoretically compared with other receiver architectures by using a WPT system model including all con... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK