# IEEE Transactions on Circuits and Systems I: Regular Papers

## Volume 65 Issue 6 • June 2018

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## Filter Results

Displaying Results 1 - 25 of 29

Publication Year: 2018, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2018, Page(s): C2
| PDF (78 KB)
• ### How to Make Analog-to-Information Converters Work in Dynamic Spectrum Environments With Changing Sparsity Conditions

Publication Year: 2018, Page(s):1775 - 1784
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Compressed sensing (CS) analog to information converters (AICs) offer key benefits for signal reception or detection when the input signal is sparse. So far AICs have been demonstrated in environments with controlled input signal conditions and with fixed sparsity levels. This paper investigates how to make AICs effectively operate in dynamic environments with changing signal conditions and thus c... View full abstract»

• ### A 250-MHz Pipelined ADC-Based$f_{S}/4$Noise-Shaping Bandpass ADC

Publication Year: 2018, Page(s):1785 - 1794
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A new fS/4 bandpass ΔΣ-analog-to-digital converter (ADC) architecture is realized by feeding back the delayed quantization noise inherently produced by a pipelined ADC. Designed in a 55-nm global foundry (GF) LP-CMOS process, the prototype ADC sampling at 250 MHz achieves an Signal-to-Noise+Distortion Ratio of 72, 75.8, 80.1, and 85.3 dB in a 15.64-, 7.82-, 3.91-, and 1.953-MHz band, re... View full abstract»

• ### A Fully Isolated Amplifier Based on Charge-Balanced SAR Converters

Publication Year: 2018, Page(s):1795 - 1804
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A galvanic isolated amplifier based on SAR converters architecture is presented which realizes chip level isolation in both the power and signal domains. The compact IC package contains an integrated isolated power converter which includes on-chip transformer, oscillator and rectifier, digital isolators based on on-chip transformers, a front-end programmable gain amplifier, a SAR ADC, a complement... View full abstract»

• ### Design of High-Order Type-II Delay-Locked Loops With a Fast-Settling-Zero-Overshoot Step Response and Large Jitter-Rejection Capabilities

Publication Year: 2018, Page(s):1805 - 1818
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In this paper, a design method for high-order delay-lock loops (DLLs) is presented and verified through simulations and physical experiments. The general approach is based on selecting the closed-loop transfer function of the DLL, together with identifying the coefficients of the phase-detector and voltage-controlled delay line, and subsequently, solving for parameters of the loop filter of the DL... View full abstract»

• ### Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology

Publication Year: 2018, Page(s):1819 - 1829
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This paper presents an analysis based on the impulse sensitivity function to precisely characterize and estimate the jitter caused by the common-mode interference (CMI). Unlike the conventional common-mode rejection ratio concept, the proposed method considers the CMI jitter in a transient rather than in an ac perspective. Inspired by the analytical results, we propose a clock receiver circuit (CR... View full abstract»

• ### A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization

Publication Year: 2018, Page(s):1830 - 1839
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A digital phase-locked loop (DPLL) with the background supply voltage sensitivity minimization is presented. By using a frequency subtractor, a digital supply voltage sensitivity controller can suppress the supply voltage sensitivity of a DPLL. This DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.006 mm<sup>2</sup>where the supply voltage sensitivity controller occupi... View full abstract»

• ### Analytic and Numerical Study of TCSC Devices: Unveiling the Crucial Role of Phase-Locked Loops

Publication Year: 2018, Page(s):1840 - 1849
Cited by:  Papers (1)
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This paper proposes a hybrid dynamic model of thyristor controlled series compensators (TCSCs). The objective is to demonstrate, through advanced circuit theory tools and numerical simulations that some modeling aspects are not properly taken into account in the existing literature. In particular, we consider those related to the role of the TCSC impedance when the line current is polluted by harm... View full abstract»

• ### A SiGe BiCMOS Concurrent K/V Dual-Band 16-Way Power Divider and Combiner

Publication Year: 2018, Page(s):1850 - 1861
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A new dual-band 16-way power divider and combiner on a 0.18-μm SiGe BiCMOS process that works concurrently over 18-26 GHz (K-band) and 57-64 GHz (V-band) is presented. The 16-way K/V dual-band power divider integrates a two-way K/V dual-band Wilkinson-based power divider with a high-pass filter and multiple broad-band two-way lumpedelement and transmission-line Wilkinson power dividers. The two-wa... View full abstract»

• ### Theory and Design of Frequency-Tunable Absorptive Bandstop Filters

Publication Year: 2018, Page(s):1862 - 1874
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Absorptive bandstop filters are a relatively new class of bandstop filter, which are able to achieve very high levels of stopband rejection with relatively low-quality-factor resonators, in contrast to typical reflective bandstop filters, whose stopband rejections are limited by the quality factors of their resonators. This paper performs an in-depth theoretical and practical analysis of this clas... View full abstract»

• ### Planar Balanced-to-Unbalanced In-Phase Power Divider With Wideband Filtering Response and Ultra-Wideband Common-Mode Rejection

Publication Year: 2018, Page(s):1875 - 1886
Cited by:  Papers (1)
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Out-of-phase balanced-to-unbalanced (B2U) power dividers are popular. However, here we present a new in-phase B2U power divider, which is rarely considered. The presented power divider realizes ultrawideband common-mode suppression, while two additional transmission zeros are added around the edges of the passband, exhibiting wideband filtering response. The circuit schematic is simply composed of... View full abstract»

• ### An On-Chip CMOS Temperature Sensor Using Self-Discharging P-N Diode in a$\Delta$-$\Sigma$Loop

Publication Year: 2018, Page(s):1887 - 1896
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A CMOS temperature sensor to monitor on-chip distributed thermal profile of high-performance system-on-chips (SoCs) is presented. The architecture of this sensor utilizes a self-discharging p-n diode to implement a first-order delta-sigma (Δ-Σ) loop. To determine the on-chip temperature, the temperature-dependent reverse-bias leakage current of the diode is measured. The sensor is implemented in a... View full abstract»

• ### A Scalable Low-Power Reconfigurable Accelerator for Action-Dependent Heuristic Dynamic Programming

Publication Year: 2018, Page(s):1897 - 1908
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Adaptive dynamic programming (ADP) is an effective algorithm that has been successfully deployed in various control tasks. For many emerging applications where power consumption is a major design consideration, the conventional way of implementing ADP as software executing on a general-purpose processor is not sufficient. This paper proposes a scalable and low-power hardware architecture for imple... View full abstract»

• ### A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation

Publication Year: 2018, Page(s):1909 - 1918
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Nowadays, the high power density and the process, voltage, and temperature variations became the most critical issues that limit the performance of the digital integrated circuits because of the continuous scaling of the fabrication technology. Dynamic voltage and frequency scaling technique is used to reduce the power consumption while different error recovery techniques are used to tolerate the ... View full abstract»

• ### VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting

Publication Year: 2018, Page(s):1919 - 1928
Cited by:  Papers (1)
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Spin-torque-transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of STTRAM poses serious challenge to sensing. We propose a non-destructive and low-power sensing scheme that exploits a voltage feedback and boosting technique to develop large sense margin. Monte Carlo simulation results in ST Microelec... View full abstract»

• ### Modular Design of High-Efficiency Hardware Median Filter Architecture

Publication Year: 2018, Page(s):1929 - 1940
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This paper presents the hardware design and implementation of 1-D median filter that uses modular architecture, which produces median results hierarchically. Different types of submodules could be applied to form a customized architecture in order to meet different constraints and requirements. Complete analysis and hardware-oriented optimization were performed to achieve the optimal configuration... View full abstract»

• ### Efficient Hardware Architectures for Deep Convolutional Neural Network

Publication Year: 2018, Page(s):1941 - 1953
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Convolutional neural network (CNN) is the state-of-the-art deep learning approach employed in various applications. Real-time CNN implementations in resource limited embedded systems are becoming highly desired recently. To ensure the programmable flexibility and shorten the development period, field programmable gate array is appropriate to implement the CNN models. However, the limited bandwidth... View full abstract»

• ### An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits

Publication Year: 2018, Page(s):1954 - 1967
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The computation-intensive circuit simulation makes the analog circuit sizing challenging for large-scale/complicated analog/RF circuits. A Bayesian optimization approach has been proposed recently for the optimization problems involving the evaluations of black-box functions with high computational cost in either objective functions or constraints. In this paper, we propose a weighted expected imp... View full abstract»

• ### Efficient Behavioral Simulation of Charge-Pump Phase-Locked Loops

Publication Year: 2018, Page(s):1968 - 1980
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The simulation of the full netlist of a phase locked loop (PLL) is resource demanding due to the prohibitive time needed to derive output noise, spurs, and transient performance from detailed transistor-level simulations. To overcome this limitation, behavioral models are needed but they must be accurate and time-efficient. This paper introduces a new behavioral macro-model of the charge-pump PLL,... View full abstract»

• ### NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization

Publication Year: 2018, Page(s):1981 - 1993
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Semiconductor technologies bring the possibility of embedding billions of components in a chip, allowing the design of complex integrated circuits. However, such levels of integration are not free and delay uncertainties grow steadily, which is increasingly challenging. Quasi-delay-insensitive (QDI) design promises to cope with such challenges, being less timing constrained than synchronous or bun... View full abstract»

• ### Lyapunov Conditions for Stability of Stochastic Impulsive Switched Systems

Publication Year: 2018, Page(s):1994 - 2004
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This paper studies stability of stochastic impulsive switched systems. Different from exponential Lyapunov function and average dwell-time in the previous works, general Lyapunov function and fixed dwell-time are implemented in this paper to analyze input-to-state stability and global stability of stochastic impulsive switched systems. Two cases are investigated, that is, the case that the continu... View full abstract»

• ### One Mbps 1 nJ/b 3.5–4 GHz Fully Integrated FM-UWB Transmitter for WBAN Applications

Publication Year: 2018, Page(s):2005 - 2014
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This paper introduces a fully integrated frequency-modulated ultra-wideband (UWB) transmitter implemented in 130 nm CMOS technology. The 3.5-4 GHz band transmitter involves a phase-locked loop (PLL)-based binary frequency-shift keying subcarrier generator to provide the modulated triangular waveform. The RF signal is generated using a voltage-controlled oscillator and modulated by the triangular s... View full abstract»

• ### Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis

Publication Year: 2018, Page(s):2015 - 2023
Cited by:  Papers (1)
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This paper presents the system architecture, modeling, and design constraints of a wireless chip-to-chip-communication transceiver as a low-power alternative to wireline links, such as PCI-Express. On top of the potential power savings, the wireless link provides lower latency times, better flexibility, lower complexity, and easier heat diffusion. The proposed transceiver uses impulse-radio ultra-... View full abstract»

• ### Compact Fast-Waking Light/Heat-Harvesting 0.18-$\mu\text{m}$CMOS Switched-Inductor Charger

Publication Year: 2018, Page(s):2024 - 2034
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Although microsystems can nowadays consume microwatts, onboard batteries can be so small and leaky that sustaining microwatts for months or years without recharge cycles can be virtually impossible. Tiny photovoltaic cells and thermoelectric generators can help, but only when light or heat is available, and only to the extent that light intensity and thermal gradients allow. This is why energy-har... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK