Scheduled System Maintenance
IEEE Xplore is currently undergoing scheduled maintenance.
During this time, there may be intermittent impact on performance. We apologize for any inconvenience.

# IEEE Transactions on Circuits and Systems I: Regular Papers

## Volume 65 Issue 4 • April 2018

The purchase and pricing options for this item are unavailable. Select items are only available as part of a subscription package. You may try again later or contact us for more information.

## Filter Results

Displaying Results 1 - 25 of 30

Publication Year: 2018, Page(s):C1 - C4
| PDF (172 KB)
• ### IEEE Transactions on Circuits and Systems—I:Regular Papers publication information

Publication Year: 2018, Page(s): C2
| PDF (78 KB)
• ### Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit

Publication Year: 2018, Page(s):1157 - 1173
| | PDF (7127 KB) | HTML

Analysis simplified with circuit insights reveals the major sources of distortion in a passive FET-switch-based sampling circuit: 1) $R_{\mathrm{\scriptscriptstyle ON}}$ -modulation; 2) turn-OFF-time instant; and 3) signal-dependent charge-injection. Explicit expressions for second- and third-order distortions advance intuitive understanding of the processes of distortion. Circuit simulations and ... View full abstract»

• ### An Analogue Neuromorphic Co-Processor That Utilizes Device Mismatch for Learning Applications

Publication Year: 2018, Page(s):1174 - 1184
| | PDF (2896 KB) | HTML Media

As the integrated circuit (IC) technology advances into smaller nanometre feature sizes, a fixed-error noise known as device mismatch is introduced owing to the dissimilarity between transistors, and this degrades the accuracy of analog circuits. In this paper, we present an analog co-processor that uses this fixed-pattern noise to its advantage to perform complex computation. This circuit is an e... View full abstract»

• ### Analysis and Design of a Ripple Reduction Chopper Bandpass Amplifier

Publication Year: 2018, Page(s):1185 - 1195
Cited by:  Papers (1)
| | PDF (3425 KB) | HTML

A low-power low-noise chopper amplifier for biosensor applications is proposed. To tackle the inherent ripple artifacts, it employs a simple ripple reduction method using a bandpass amplifier. The chopper amplifier is a linear periodic time-varying system. The method of harmonic transfer matrix is used to derive the signal and the noise harmonic transfer functions, and the theoretical results are ... View full abstract»

• ### A Gm-C Delta-Sigma Modulator With a Merged Input-Feedback Gm Circuit for Nonlinearity Cancellation and Power Efficiency Enhancement

Publication Year: 2018, Page(s):1196 - 1209
Cited by:  Papers (1)
| | PDF (3355 KB) | HTML

Traditionally, a transconductor-C (Gm-C)-based delta sigma modulator (DSM) has its performance limited by the nonlinearity of its Gm circuits. To achieve sufficient linearity, source degeneration is typically applied to a Gm circuit, which inevitably reduces the Gm circuit's transconductance and thermal noise efficiencies. This paper presents new ways to change this paradigm. First, a DSM topology... View full abstract»

• ### BiCMOS-Based Compensation: Toward Fully Curvature-Corrected Bandgap Reference Circuits

Publication Year: 2018, Page(s):1210 - 1223
Cited by:  Papers (1)
| | PDF (3807 KB) | HTML

We present a novel BiCMOS-based temperature compensation technique aiming at complete correction of the curvature in the temperature response of bandgap references. The source of the appearance of this curvature is because the well-known nonlinear term T ln(T) in the base-emitter voltage (VBE) is not completely canceled across all temperature points. Here, we show that the gate-source v... View full abstract»

• ### A Low Noise Low Offset Readout Circuit for Magnetic-Random-Access-Memory

Publication Year: 2018, Page(s):1224 - 1233
| | PDF (1858 KB) | HTML

A unique readout circuit topology aimed at integration with a novel type of magnetic random access memory (MRAM) is presented. The properties of the new MRAM bitcell are introduced, and the specifics of the circuit used to interface with the CMOS circuitry are described. The noise transfer function and effectiveness of the proposed topology with its practical limitations are discussed. Post-silico... View full abstract»

• ### Novel Time-Domain Schottky Diode Modeling for Microwave Rectifier Designs

Publication Year: 2018, Page(s):1234 - 1244
Cited by:  Papers (1)
| | PDF (2373 KB) | HTML

A novel modeling methodology of Schottky diode for microwave rectifier design is proposed in this paper. The challenge was to consider the effective capacitance of the diode under different status being usually ignored in previous works. In addition, the charging and discharging behaviors causing extra power consumption had been considered for a higher modeling accuracy. To improve the diode model... View full abstract»

• ### A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI

Publication Year: 2018, Page(s):1245 - 1256
Cited by:  Papers (2)
| | PDF (4717 KB) | HTML

Gain-cell embedded DRAM (GC-eDRAM) is a possible alternative to traditional static random access memories (SRAM). While GC-eDRAM provides high-density, low-leakage, low-voltage, and inherent2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further aggravated at scaled technologies, where increased subthreshold leakage currents and decre... View full abstract»

• ### A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD–SOI

Publication Year: 2018, Page(s):1257 - 1268
Cited by:  Papers (2)
| | PDF (2920 KB) | HTML

A 128-kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in 28-nm FD-SOI technology is presented. An ideal power management scenario in a single supply system is achieved by permanently keeping the storage elements in the vicinity of the retention voltage. Performance and reliability is regained by boosting the voltage on critical nodes. The cost of voltage boost genera... View full abstract»

• ### Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs

Publication Year: 2018, Page(s):1269 - 1278
Cited by:  Papers (3)
| | PDF (1762 KB) | HTML

This paper proposes a novel approach to enhance the STT-MRAMs read margin based on the concept of dynamic reference (DR). Our dynamic reference scheme dynamically adjusts the sense amplifier reference voltage according to the bitline voltage, aiming to widen the difference between the bitline and the reference voltage (i.e., the read margin). As a result, larger variations can be accommodated, thu... View full abstract»

• ### True Random Number Generator Based on Flip-Flop Resolve Time Instability Boosted by Random Chaotic Source

Publication Year: 2018, Page(s):1279 - 1292
| | PDF (5132 KB) | HTML

This paper introduces a new concept of a true random number generator (TRNG) based on two stages of randomness. The first stage is based on a novel chaotic circuit, which utilizes time as a continuous random variable in a feedback loop. The second stage is based on metastability; however, in contrast to known digital solutions, a flip-flop is stimulated by chaotic initial conditions. The advantage... View full abstract»

• ### Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection

Publication Year: 2018, Page(s):1293 - 1302
| | PDF (1772 KB) | HTML

Soft errors produced by radiation events can cause malfunctions in modern day electronics. To preserve the system functionality, its elements must be protected against the effects of these events. Two of the possible techniques usually employed to implement fault tolerant registers are triple modular redundancy (TMR) and single error correcting (SEC) codes. However, the use of these techniques inc... View full abstract»

• ### A Variational Approach for Designing Infinite Impulse Response Filters With Time-Varying Parameters

Publication Year: 2018, Page(s):1303 - 1313
Cited by:  Papers (1)
| | PDF (3202 KB) | HTML

Filter design with short transient state is a problem encountered in many fields of circuits, systems, and signal processing. In this paper, a novel low-pass filter design technique with time-varying parameters is introduced in order to minimize the rise-time parameter. Through the use of calculus of variations a method is developed to obtain the optimal closed-form expression for adjusting the pa... View full abstract»

• ### Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning

Publication Year: 2018, Page(s):1314 - 1326
Cited by:  Papers (1)
| | PDF (3696 KB) | HTML

Edge analytics support industrial Internet of Things by pushing some data processing capacity to the edge of the network instead of sending the streaming data captured by the sensor nodes directly to the cloud. It is advantageous to endow machine learners for data reduction with suitable security primitives for privacy protection in edge computing devices to conserve area and power consumption. In... View full abstract»

• ### Memristor Circuits: Pulse Programming via Invariant Manifolds

Publication Year: 2018, Page(s):1327 - 1339
Cited by:  Papers (3)
| | PDF (8447 KB) | HTML

This paper considers a large class of memristor circuits of arbitrary order, and containing an arbitrary number of flux- or charge-controlled memristors, for which a state equation (SE) description can be obtained. By means of the SEs, it is shown that the state space of each circuit can be decomposed in infinitely many manifolds, and that in the autonomous case, each manifold is positively invari... View full abstract»

• ### Power-Handling Capacity and Nonlinearity Analysis for Distributed Electronic Impedance Synthesizer

Publication Year: 2018, Page(s):1340 - 1348
Cited by:  Papers (1)
| | PDF (3770 KB) | HTML

With advantages of small size, light weight, and fast tuning capability, electronic impedance synthesizer (EIS) presents game-changing opportunities for industry. However, their widely acceptance is still restrained by the understanding of power-handling capacity and linearity issues. This work addresses both issues through the development of a voltage distribution theory which enables simulating ... View full abstract»

• ### An Architecture to Accelerate Convolution in Deep Neural Networks

Publication Year: 2018, Page(s):1349 - 1362
Cited by:  Papers (2)
| | PDF (3035 KB) | HTML

In the past few years, the demand for real-time hardware implementations of deep neural networks (DNNs), especially convolutional neural networks (CNNs), has dramatically increased, thanks to their excellent performance on a wide range of recognition and classification tasks. When considering real-time action recognition and video/image classification systems, latency is of paramount importance. T... View full abstract»

• ### Wave-Based Analysis of Large Nonlinear Photovoltaic Arrays

Publication Year: 2018, Page(s):1363 - 1376
Cited by:  Papers (4)
| | PDF (2793 KB) | HTML

In this paper, a novel analysis method based on wave digital (WD) principles is presented. The method is employed for modeling and efficiently simulating large photovoltaic (PV) arrays under partial shading conditions. The WD method allows rapid exploration of the current-voltage curve at the load of the PV array, given: the irradiation pattern, the nonlinear PV unit model (e.g., exponential junct... View full abstract»

• ### Cooperative Output Regulation of Singular Multi-Agent Systems Under Switching Network by Standard Reduction

Publication Year: 2018, Page(s):1377 - 1385
| | PDF (915 KB) | HTML

The cooperative output regulation problem for singular multi-agent systems subject to static networks was studied recently under the assumption that each follower system satisfies the standard assumption. In this paper, we further study the same problem for singular multi-agent systems subject to jointly connected switching networks. First, by introducing a static output feedback control, we remov... View full abstract»

• ### Event-Based Control for Network Systems via Integral Quadratic Constraints

Publication Year: 2018, Page(s):1386 - 1394
Cited by:  Papers (2)
| | PDF (1120 KB) | HTML

This paper investigates the event-based control for network systems. Edge-based approach is utilized to predict the value of edge state between two event instants. Different from the node-based approach, it can significantly reduce the communication burden at event instants. Based on the small gain theorem, the closed-loop system is expressed as the feedback interconnection of a linear time-invari... View full abstract»

Publication Year: 2018, Page(s):1395 - 1405
| | PDF (1325 KB) | HTML

In this paper, we design a no-overloading error feedback quantizer based on a AΣ modulator, composed of an error feedback filter and a static quantizer. To guarantee no-overloading in the quantizer, we impose an l∞norm constraint on the feedback signal in the quantizer. Then, for a prescribed l∞norm constraint on the error at the system output induced by the quantizer, we des... View full abstract»

• ### A Millimeter-Wave Fully Integrated Passive Reflection-Type Phase Shifter With Transformer-Based Multi-Resonance Loads for 360&#x00B0; Phase Shifting

Publication Year: 2018, Page(s):1406 - 1419
Cited by:  Papers (4)
| | PDF (8192 KB) | HTML

This paper presents a millimeter-wave fully differential transformer-based passive reflection-type phase shifter (RTPS) capable of performing full span 360&#x00B0; continuous phase shift from 58 to 64 GHz. It consists of two transformerbased 90&#x00B0; couplers and two transformer-based multi-resonance reflective loads to provide 360&#x00B0; phase shift with low loss and ultra-compact ... View full abstract»

• ### A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture

Publication Year: 2018, Page(s):1420 - 1431
Cited by:  Papers (1)
| | PDF (2436 KB) | HTML

Powerful forward error correction (FEC) schemes are used in optical communications to achieve bit-error rates (BERs) below 10-15. These FECs follow one of two approaches: the concatenation of simpler hard-decision codes or the usage of inherently powerful soft-decision codes. The first approach yields lower net coding gains (NCGs), but can usually work at higher code rates and have lowe... View full abstract»

## Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Andreas Demosthenous
Dept. Electronic & Electrical Engineering
University College London
London WC1E 7JE, UK